A CMOS 65nm On-Chip RF Inductor with Hybrid Spiral-Meander Layout Optimization and Ferroelectric Stack-Up Integration for Q-Factor Enhancement Manibharathee Muniandy, Selvakumar Mariappan*, Jagadheswaran Rajendran, Norhamizah Idros, Asrulnizam Abdul Manaf, Narendra Kumar, Arokia Nathan, 10.57647/j.mjee.2025.17414 XML Requires Subscription PDF downloads: 336
A 16-Level Digital Trimmable CMOS 65nm Bandgap Reference with Process, Voltage, and Temperature Stability Guo Li Ng, Jagadheswaran Rajendran*, Selvakumar Mariappan, Norhamizah Idros, Asrulnizam Abdul Manaf, Narendra Kumar, Arokia Nathan, 10.57647/j.mjee.2025.18026 XML Requires Subscription PDF downloads: 244
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10.57647/j.mjee.2025.18026
