10.57647/j.mjee.2025.17414

A CMOS 65nm On-Chip RF Inductor with Hybrid Spiral-Meander Layout Optimization and Ferroelectric Stack-Up Integration for Q-Factor Enhancement

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  • Manibharathee Muniandy1,
  • Selvakumar Mariappan*1,
  • Jagadheswaran Rajendran1,
  • Norhamizah Idros1,
  • Asrulnizam Abdul Manaf1,
  • Narendra Kumar2,
  • Arokia Nathan3,
  1. Collaborative Microelectronics Design Excellence Centre (CEDEC), Universiti Sains Malaysia, Penang 11900, Malaysia
  2. Department of Electrical Engineering, Faculty of Engineering, University of Malaya, Kuala Lumpur, Malaysia
  3. Darwin College, Cambridge University, Silver Street, Cambridge CB3 9EU, UK

Received: 2025-05-23

Revised: 2025-07-10

Accepted: 2025-07-22

Published in Issue 2025-09-01

Copyright (c) 2025 Manibharathee Muniandy, Selvakumar Mariappan, Jagadheswaran Rajendran, Norhamizah Idros, Asrulnizam Abdul Manaf, Narendra Kumar, Arokia Nathan (Author)

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This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

Muniandy, M., Mariappan, S., Rajendran, J., Idros, N., Manaf, A. A., Kumar, N., & Nathan, A. (2025). A CMOS 65nm On-Chip RF Inductor with Hybrid Spiral-Meander Layout Optimization and Ferroelectric Stack-Up Integration for Q-Factor Enhancement. Majlesi Journal of Electrical Engineering. https://doi.org/10.57647/j.mjee.2025.17414
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Abstract

On-chip inductors are crucial for enhancing the functionality of microelectronic devices, particularly in wireless communication. Still, traditional designs often lead to increased chip size and reduced performance due to their bulkiness and integration challenges. By utilizing an electromagnetic (EM) simulation tool, this research presents a novel on-chip inductor design optimized for 65 nm CMOS technology, achieving an inductance of 3.2 nH with a Q-factor of 15.31 at 1.7 GHz. The primary contributor to the Q-factor enhancement is the layout optimization techniques, which improve the Q-factor by approximately 21%. Additionally, further improvements in inductance and Q-factor are achieved by integrating Nickel Zinc Cobalt-based ferroelectric liquid materials into the simulation stack-up layer. This material stack-up serves as a secondary contributor, enhancing the magnetic properties of the inductor and increasing the Q-factor to 15.83 which is an additional 6% improvement over the proposed design. The proposed layout optimization and material innovations demonstrate the potential for achieving higher inductance values and Q-factors, effectively addressing the limitations of conventional methods. The results highlight the feasibility of incorporating advanced materials in on-chip inductor design, paving the way for next-generation RF integrated circuits that meet the growing demands for miniaturization and energy efficiency in modern electronics.

Keywords

  • CMOS,
  • Inductor,
  • Q-Factor,
  • Layout Optimization,
  • Ferroelectric
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References

  1. A. Daghighi and A. R. Neshat-Niko, “VCO design and simulation using TSMC 0.18 μm process to meet IEEE802.11a requirements,” Majlesi J. Electr. Eng., vol. 2, no. 2, Feb. 2024, doi: 10.1234/mjee.v2i2.56.
  2. F. Shirani Bidabadi and S. V. Mir-Moghtadaei, “Low power broadband sub-GHz CMOS LNA with 1 GHz bandwidth for IoT application,” Majlesi J. Electr. Eng., vol. 16, no. 4, 2022, doi: 10.30486/mjee.2022.696519.
  3. M. Jalalifar, M. Yavari, and F. Raissi, “A novel frequency compensation technique in three stage amplifiers with active feedback,” Majlesi J. Electr. Eng., vol. 4, no. 1, Feb. 2024, doi: 10.1234/mjee.v4i1.216.
  4. A. Bhaskar, S. Kumar, P. Singh, R. Sharma, and V. Gupta, “Substrate engineering of inductors on SOI for improvement of Q-factor and application in LNA,” IEEE J. Electron Devices Soc., vol. 8, pp. 959–969, Jan. 2020, doi: 10.1109/JEDS.2020.3019884.
  5. I. Kadyan, M. Kumar, and A. P. Singh, “Design and analysis of a novel 90 nm tunable active-inductor with high Q-factor in LC-VCO for C and Ku band,” Eng. Res. Express, vol. 7, no. 1, Art. no. 015372, Mar. 2025, doi: 10.1088/2631-8695/adbcfb.
  6. N. S. Yusof, M. H. Ibrahim, A. Z. Abidin, and R. M. Sidek, “Patterned ground shield for inductance fine-tuning,” IETE J. Res., vol. 68, no. 4, pp. 2764–2778, Feb. 2020, doi: 10.1080/03772063.2020.1726827.
  7. J.-N. Wu, Y.-M. Chang, Z.-Y. Shen, and H.-C. Chen, “Investigation on CMOS on-chip inductors using various patterned ground/floating shield techniques,” in Proc. Int. Conf. Electron. Commun., IoT Big Data (ICEIB), Yilan County, Taiwan, 2021, pp. 113–116, doi: 10.1109/ICEIB53692.2021.9686404.
  8. S. Spataro, N. Salerno, G. Papotto, and E. Ragonese, “The effect of a metal PGS on the Q-factor of spiral inductors for RF and mm-wave applications in a 28 nm CMOS technology,” Int. J. RF Microw. Comput.-Aided Eng., vol. 30, no. 10, Aug. 2020, doi: 10.1002/mmce.22368.
  9. N. K.-S. Chen, A. A. Ayon, N. X. Zhang, and S. M. Spearing, “Effect of process parameters on the surface morphology and mechanical performance of silicon structures after deep reactive ion etching (DRIE),” J. Microelectromech. Syst., vol. 11, no. 3, pp. 264–275, Jun. 2002, doi: 10.1109/JMEMS.2002.1007405.
  10. O. F. Hikmat and M. S. M. Ali, “RF MEMS inductors and their applications—A review,” J. Microelectromech. Syst., vol. 26, no. 1, pp. 17–44, Feb. 2017, doi: 10.1109/JMEMS.2016.2627039.
  11. J. Kang, Y. Matsumoto, X. Li, J. Jiang, X. Xie, K. Kawamoto, M. Kenmoku, J. H. Chu, W. Liu, J. Mao, and K. Ueno, “On-chip intercalated-graphene inductors for next-generation radio frequency electronics,” Nat. Electron., vol. 1, no. 1, pp. 46–51, Jan. 2018, doi: 10.1038/s41928-017-0010-z.
  12. C. Sun, D. Qiu, P. Li, Z. Yao, W. Zong, and S. Li, “Inductance and Q-factor of micromagnetic inductor are enhanced by FeCoB films with self-bias,” Phys. Status Solidi RRL, vol. 19, no. 1, p. 2400167, Jan. 2025, doi: 10.1002/pssr.202400167.
  13. S. Salleh, K. Salleh, M. F. Hashim, and Z. Abd. Majid, “Design and analysis of 13.56 MHz RFID antenna based on modified Wheeler equation: A practical approach,” in Proc. Int. Conf. Electron. Devices, Syst. Appl. (ICEDSA), Kuala Lumpur, Malaysia, 2010, pp. 326–330, doi: 10.1109/ICEDSA.2010.5503048.
  14. A. Alkasir, S. E. Abdollahi, S. Abdollahi, and P. Wheeler, “Analytical modeling of self-and mutual inductances of DD coils in wireless power transfer applications,” J. Electromagn. Eng. Sci., vol. 22, no. 2, pp. 162–170, 2022, doi: 10.26866/jees.2022.2.r.73.
  15. E. S. Mawuli, Y. Wu, D. K. B. Kulevome, Z. Qingfeng, C. Zhao, H. Liu, and K. Kai, “Distributed characterization of on-chip spiral inductors for millimeter-wave frequencies,” in Proc. IEEE MTT-S Int. Conf. Numer. Electromagn. Multiphys. Modeling Optim. (NEMO), Dec. 2020, pp. 1–4, doi: 10.1109/NEMO49486.2020.9343469.
  16. R. Sai, R. D. R. Kahmei, S. A. Shivashankar, and M. Yamaguchi, “High-Q on-chip C-band inductor with a nanocrystalline MNZN-ferrite film core,” IEEE Trans. Magn., vol. 55, no. 7, pp. 1–4, Jul. 2019, doi: 10.1109/TMAG.2019.2916699.
  17. A. Saini, P. Kumar, B. Ravelo, S. Lallechere, A. Thakur, and P. Thakur, “Magneto-dielectric properties of doped ferrite-based nanosized ceramics over very high frequency range,” Eng. Sci. Technol. Int. J., vol. 19, no. 2, pp. 911–916, Apr. 2016, doi: 10.1016/j.jestch.2015.12.008.
  18. M. Wang, W. Li, X. Zuo, W. Zhu, and G. Zhang, “Structure and dielectric properties of barium strontium titanate ferroelectric thin film prepared by DC micro-arc oxidation,” Appl. Phys. A, vol. 126, pp. 1–8, 2020, doi: 10.1007/s00339-020-03937-0.
  19. O. M. Hemeda, B. I. Salem, and M. Mostafa, “Structural and electric properties of strontium barium titanate prepared by tartrate precursor method,” Eur. Phys. J. Plus, vol. 135, no. 1, pp. 1–15, 2020, doi: 10.1140/epjp/s13360-019-00021-2.
  20. P. Goel, K. L. Yadav, and A. R. James, “Double doping effect on the structural and dielectric properties of PZT ceramics,” J. Phys. D: Appl. Phys., vol. 37, no. 22, p. 3174, 2004, doi: 10.1088/0022-3727/37/22/019.
  21. S. B. Cho, D. H. Kang, and J. H. Oh, “Relationship between magnetic properties and microwave-absorbing characteristics of NiZnCo ferrite composites,” J. Mater. Sci., vol. 31, pp. 4719–4722, 1996, doi: 10.1007/BF00366375.
  22. H.-H. Chen and Y.-W. Hsu, “Analytic design of on-chip spiral inductor with variable line width,” Electronics, vol. 11, no. 13, p. 2029, Jun. 2022, doi: 10.3390/electronics11132029.
  23. A. Thakur and S. Chatterjee, “Design of a monolithic inductor and its influence on the oscillator design,” IETE J. Res., vol. 68, no. 3, pp. 2238–2245, Dec. 2019, doi: 10.1080/03772063.2019.1696715.
  24. H. Bouyghf, B. Benhala, and A. Raihani, “Analysis of the impact of metal thickness and geometric parameters on the quality factor-Q in integrated spiral inductors by means of artificial bee colony technique,” Int. J. Electr. Comput. Eng., vol. 9, no. 4, pp. 2918–2931, Aug. 2019, doi: 10.11591/ijece.v9i4.pp2918-2931.
  25. R. Ondica, M. Kovac, A. Hudec, R. Ravasz, D. Maljar, V. Stopjakova, and D. Arbet, “An overview of fully on-chip inductors,” Radioengineering, vol. 32, no. 1, p. 11, 2023, doi: 10.13164/re.2023.0011.
  26. H. Chen, X. Wang, Y. Gao, X. Shi, Z. Wang, N. Sun, M. Zaeimbashi, X. Liang, Y. He, C. Dong, and Y. Wei, “Integrated tunable magnetoelectric RF inductors,” IEEE Trans. Microw. Theory Techn., vol. 68, no. 3, pp. 951–963, Mar. 2020, doi: 10.1109/TMTT.2019.2957472.