A Digital Ground Distance Relaying Algorithm to Reduce the Effect of Fault Resistance during Single Phase to Ground and Simultaneous Faults

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  • Mohammad Razaz1,
  • Seyyed Ghodratollah Seifossadat1,
  • Morteza Razaz1,
  • Mahmood Joorabian2,
  1. Department of Electrical Engineering, Shahid Chamran University of Ahvaz, Iran
  2. Department of Electrical Engineering, Shahid Chamran University, Ahvaz, Iran

Published in Issue 2024-02-20

How to Cite

Razaz, M., Seifossadat, S. G., Razaz, M., & Joorabian, M. (2024). A Digital Ground Distance Relaying Algorithm to Reduce the Effect of Fault Resistance during Single Phase to Ground and Simultaneous Faults. Majlesi Journal of Electrical Engineering, 9(1). https://oiccpress.com/mjee/article/view/5303

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Abstract

This paper intends to provide an algorithm of fault resistance compensation for digital ground distance relay considering the voltage and current transformer effects. Performance of the conventional ground distance relaying manner is adversely affected by different ground faults and also typical type, called a simultaneous open conductor and ground fault. The proposed scheme by using local-end data only, has shown satisfactory performances under wide variations in fault location, with different values of fault resistance and having positive and negative of power transfer angle. The presented method which has been carried out on the IEEE 14 bus benchmark is executed in PSCAD/EMTDC and MATLAB software and the results show the accurate performance of mention configuration.

Keywords

  • Digital Ground Distance Relaying,
  • Fault Resistance Compensation,
  • Simultaneous Open Conductor and Ground Fault,
  • Single Phase to Ground Fault,
  • Voltage and Current Transformer
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