Design Issues for Low Voltage Low Power CMOS Folded Cascode LNAs

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  • Ehsan Kargaran1,
  • Mohammad Javad Zavarei2,
  • Nahid Fatahi2,
  • Seyedeh Sara Hassani2,
  • Khalil Mafinezhad3,
  • Hooman Nabovati4,
  1. sadjad institue of higher education, mashhad
  2. Microelectronic Laboratory, Sadjad Institute of Higher Education, Mashhad, Iran
  3. Sadjad Institute of Higher Education, Mashhad, Iran
  4. Department of Electrical Engineering, Sadjad Institute of Higher Education, Mashhad

Published in Issue 2024-02-25

How to Cite

Kargaran, E., Zavarei, M. J., Fatahi, N., Hassani, S. S., Mafinezhad, K., & Nabovati, H. (2024). Design Issues for Low Voltage Low Power CMOS Folded Cascode LNAs. Majlesi Journal of Electrical Engineering, 6(3). https://oiccpress.com/mjee/article/view/5212

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Abstract

Design and simulation results of fully integrated 5-GHz CMOS LNAs are presented in this paper. Three different input impedance matching techniques are considered. Using a simple L-C network, the parasitic input resistance of a MOSFET is converted to a 50 Ω resistance. As it is analytically proven, that is because the former methods enhance the gain of the LNA by a factor that is inversely proportional to MOSFETâs input resistance. The effect of each input impedance matching on the amplifierâs noise figure and gain is discussed. By employing the folded cascode configuration, these LNAs can operate at a reduced supply voltage and thus lower power consumption. To address the issue of nonlinearity in design of low voltage LNAs, a new linearization technique is employed. As a result, the IIP3 is improved extensively without sacrificing other parameters. These LNAs consume 1.3 mW power under a 0.6 V supply voltage.

Keywords

  • reliability. Technical feasibility
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