10.57647/j.mjee.2025.17413

Design of 65nm 6T SRAM Using Improved Sense Amplifiers and Write Driver Circuits

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  • Quang Vinh Truong*1,
  • Tuan Dat Tieu1,
  1. Faculty of Electrical and Electronics Engineering, Ho Chi Minh City University of Technology, Vietnam National University – Ho Chi Minh, Ho Chi Minh City, Vietnam

Received: 2025-04-30

Revised: 2025-07-07

Accepted: 2025-07-19

Published in Issue 2025-09-25

Published Online: 2025-09-01

Copyright (c) 2025 Quang Vinh Truong, Tuan Dat Tieu (Author)

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

Truong, Q. V., & Tieu, T. D. (2025). Design of 65nm 6T SRAM Using Improved Sense Amplifiers and Write Driver Circuits. Majlesi Journal of Electrical Engineering, 19(3 (September 2025). https://doi.org/10.57647/j.mjee.2025.17413
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Abstract

Designing high-speed 6T SRAM for efficient read and write operations poses a significant challenge for circuit designers. In this paper, we propose a 65nm 6T SRAM architecture using sense amplifiers and write driver circuits to enhance the read and write performance. The sense amplifier helps the reading process go faster and the reading data be more stable. The write driver is designed with a symmetrical structure to reduce the write delay. In addition, the control circuit performs the checking process to synchronize read operations, optimize latency without interruption. The simulation result shows that the read delay and write delay are 58.66ps and 79.67ps, respectively. These delays outperform most of the other study.

Keywords

  • Static random-access memory,
  • Sense amplifier,
  • Write driver circuit,
  • Complementary metal oxide semiconductor,
  • 65nm
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References

  1. N. H. E. Weste and D. M. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4th ed. Boston, MA, USA: Addison Wesley, 2010.
  2. M. K. Srivastav, Rimjhim, R. Mishra, A. Grover, K. J. Dhori, and H. Rawat, “3-Stage pipelined hierarchical SRAMs with burst mode read in 65nm LSTP CMOS,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), 2022, pp. 1–5.
  3. N. Rathi, A. Kumar, N. Gupta, and S. K. Singh, “A review of low-power static random access memory (SRAM) designs,” in Proc. IEEE Devices Integr. Circuit (DevIC), Kalyani, India, 2023, pp. 455–459.
  4. J. K. Mishra, P. K. Misra, and J. K. Srivastava, “Analytical modelling and design of 9T SRAM cell with leakage control technique,” Analog Integr. Circuits Signal Process., vol. 101, no. 1, pp. 31–43, 2019.
  5. S. Pal, S. Bose, W. H. Ki, and A. Islam, “Characterization of half-select free write assist 9T SRAM cell,” IEEE Trans. Electron Devices, vol. 66, no. 11, pp. 4745–4752, Nov. 2019.
  6. B. Zeinali, J. K. Madsen, P. Raghavan, and F. Moradi, “Sub-threshold SRAM design in 14 nm FinFET technology with improved access time and leakage power,” in Proc. IEEE Annu. Symp. VLSI (ISVLSI), Montpellier, France, 2015, pp. 74–79.
  7. S. Bagali, B. Sravani, B. Kavya, M. B. Varalakshmi, and S. L. A. Reddy, “Design and parametric analysis of 6T SRAM using 180nm and 45nm technology,” in Proc. Int. Conf. Netw., Multimedia Inf. Technol. (NMITCON), Bengaluru, India, 2023, pp. 1–7.
  8. M. Abhiram and B. M. M. Tripathi, “Performance evaluation of 9T and 6T SRAM cells at 7nm technology,” in Proc. Int. Conf. Comput. Commun. Netw. Technol. (ICCCNT), Delhi, India, 2023, pp. 1–4.
  9. A. Siddik, S. Pujari, J. Mallidu, P. Chandaragi, A. Huded, and N. Lakkundi, “Performance analysis of CMOS SRAM 6T, 7T and 9T cells using Cadence at 180nm technology,” in Proc. Int. Conf. Innov. Technol. (INOCON), Bangalore, India, 2024, pp. 1–5.
  10. T. Kalpana, C. L. Reddy, B. Saranya, and P. Naveen, “A low voltage 6T SRAM cell design and analysis using Cadence 90nm and 45nm CMOS technology,” in Proc. Int. Conf. Devices, Circuits Syst. (ICDCS), Coimbatore, India, 2024, pp. 188–194.