10.57647/j.mjee.2025.17276

FPGA-Accelerated Bird Detection Algorithm for Paddy Farmers

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  • Muhamad Ili Firdaus Mohamad Sa’ad1,
  • Rizalafande Che Ismail*2,3,
  • Siti Zarina Md Naziri2,3,
  • Mohd Nazrin Md Isa2,3,
  • Ahmad Husni Mohd Shapri2,3,
  1. Altera Corporation, Bayan Lepas Technoplex, 11900 Penang, Malaysia
  2. Centre of Excellence for Micro System Technology, Universiti Malaysia Perlis, 02600 Arau Perlis Malaysia
  3. Faculty of Electronic Engineering and Technology, Universiti Malaysia Perlis, 02600 Arau Perlis Malaysia

Received: 2025-05-05

Revised: 2025-06-28

Accepted: 2025-07-14

Published in Issue 2025-08-04

Copyright (c) 2025 Muhamad Ili Firdaus Mohamad Sa’ad, Rizalafande Che Ismail, Siti Zarina Md Naziri, Mohd Nazrin Md Isa, Ahmad Husni Mohd Shapri (Author)

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

Mohamad Sa’ad, M. I. F., Che Ismail, R., Md Naziri, S. Z., Md Isa, M. N., & Mohd Shapri, A. H. (2025). FPGA-Accelerated Bird Detection Algorithm for Paddy Farmers. Majlesi Journal of Electrical Engineering. https://doi.org/10.57647/j.mjee.2025.17276
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Abstract

Paddy farmers face significant challenges from bird pests, particularly species like pipits and sparrows, which can reduce yields by up to 70%, especially during the grain-filling stage, leading to substantial economic losses. Traditional methods of pest control, such as physical barriers, scare tactics, and chemical deterrents, are often inefficient and labour-intensive. To address this issue, this research develops an artificial intelligence (AI)-based bird detection system to protect paddy fields. The solution involves using Field-Programmable Gate Array (FPGA)-accelerated object detection models to accurately identify bird activity in real time, aligning with journal requirements for first-time abbreviation usage. The system integrates a notification mechanism via Telegram to alert farmers immediately, allowing swift manual action. The research employed the detr- resnet50 model for its precision and high confidence in detection, running on both Central Processing Unit (CPU) and FPGA configurations to optimize performance. The results showed significant improvements in latency and frames per second (FPS) when using FPGA acceleration, demonstrating effective real-time bird detection capabilities. The system’s implementation enhanced crop protection, promoted eco-friendly practices, and improved overall farming efficiency by reducing manual surveillance and providing valuable data for long-term pest management strategies. Key quantitative findings showed that FPGA acceleration improved FPS by over 200% compared to CPU performance.

Keywords

  • Artificial intelligence,
  • FPGA,
  • Object detection model,
  • Smart farming,
  • Image processing
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