Very High Throughput Implementation of Advanced Encryption Standard (AES) Algorithm on FPGA

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  • Mahdi Rahmanpour*1,
  • Amir Amirabadi Zavare1,
  1. Faculty of Electrical Engineering Islamic Azad University, South Tehran Branch Tehran, Iran

Revised: 2017-08-11

Accepted: 2017-11-12

Published in Issue 2017-12-01

How to Cite

Rahmanpour, M., & Amirabadi Zavare, A. (2017). Very High Throughput Implementation of Advanced Encryption Standard (AES) Algorithm on FPGA. Signal Processing and Renewable Energy (SPRE), 1(4), 1-8. https://oiccpress.com/spre/article/view/7756

PDF views: 188

Abstract

An Advanced Encryption Standard (AES) algorithm is one of the most popular and most commonly used encryption algorithms. This algorithm can be implemented on microcontroller chips and FPGAs with various specifications. Also, the goals of implementing this algorithm are varied according to the application and requirements. In this paper, a project has been given that output very high data transfer rate equal 192 Gbps on the FPGA of the Virtex-7 (XC7VX330T-3FFG1157) from Xilinx. The extracted results of the implementation of the algorithm in the ISE 14.7 software show the maximum achievable clock frequency 500 MHz, with the parallel implementation of than three AES algorithms cores on a chip, higher speeds are also available.
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