Power-efficient and high-speed design of approximate full adders using CNFET technology
Authors
Abstract
Full adder cells are the major fundamental elements of larger arithmetic circuits, which are mostly located along the critical path of circuits. Therefore, the design of low-power and high-speed full adder cells is critical. In this paper, there are two new inexact full adder cells proposed based on Carbon Nanotube Field Effect Transistor (CNFET) technology. Using the HSPICE simulator by applying the 32 nm Stanford model, extensive simulations are performed at the transistor level. Different supply voltages, output loads, and ambient temperatures are involved in the operation of the cells. In addition, by applying Monte Carlo transient analysis, the effects of diameter variations of carbon nanotubes (CNTs) are examined on the performance of the proposed cells. Considering the application level, these cells are studied in image processing through MATLAB software. The superiority of the proposed cells compared to their counterparts is confirmed by extensive simulations.
