A New Low Power, Area Efficient 4-bit Carry Look Ahead Adder in CNFET Technology

Authors

• Ali Ghorbani ¹
• Mehdi Dolatshahi ²
• S. Mohammadali Zanjani ³
• Behrang Barekatain ⁴

1. Faculty of Computer Engineering, Najafabad Branch, Islamic Azad University, Najafabad, Iran.
2. Department of Electrical Engineering, Najafabad Branch, Islamic Azad University, Najafabad, Iran.
3. Big Data Research Center, Najafabad Branch, Islamic Azad University, Najafabad, Iran.
4. Smart Microgrid Research Center, Najafabad Branch, Islamic Azad University, Najafabad, Iran.

Abstract

In this paper, a new hybrid low-power and area efficient Carry Look-Ahead Adder in CNFET technology based on the full-swing Gate Diffusion Input (GDI) technique is proposed. The proposed CLA design in GDI logic style, not only decreases the circuit area effectively but also decreases the power consumption and delay parameters as well. The proposed design is simulated in HSPICE using the CNFET model parameters. Finally, the simulation results justify a good improvement in the circuit performance parameters such as power consumption, delay, chip size area and power-delay product (PDP) for the proposed CLA circuit.

Keywords

• Area-efficient.
• Low-power
• Carry Look-Ahead Adder
• GDI
• CNFET