10.57647/spre.2026.1001.03

Improved PDP of the Open-Loop Phase-FrequencyDetector to Reduce the Output Jitter of Phase-Locked Loop Circuits in CMOS Technology

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  • MohammadSadegh Zarbakhsh1,
  • Behzad Ghanavati*1,
  • Pejman Shaabani1,
  • Sajad Tabatabaee Tabatabaee1,
  1. Department of Electrical Engineering, Mahs.C., Islamic Azad University, Mahshahr, Iran

Received: 2025-11-16

Revised: 2025-12-20

Accepted: 2025-12-20

Published in Issue 2026-03-31

Copyright (c) 2026 MohammadSadegh Zarbakhsh, Behzad Ghanavati, Pejman Shaabani, Sajad Tabatabaee Tabatabaee (Author)

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

Zarbakhsh, M., Ghanavati, B., Shaabani, P., & Tabatabaee, S. T. (2026). Improved PDP of the Open-Loop Phase-FrequencyDetector to Reduce the Output Jitter of Phase-Locked Loop Circuits in CMOS Technology. Signal Processing and Renewable Energy (SPRE), 10(1). https://doi.org/10.57647/spre.2026.1001.03
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Abstract

A new phase-locked loop (PLL) with an improved open-loop phase-frequency detector block (PFD) with a dead zone close to zero and a compatible charge pump (CP) to reduce the power consumption and the dead zone and output jitter is proposed. Since in all phase-locked loop systems, phase-frequency detector and charge pump elements are designed and used separately, inherently, detecting the phase difference by the phase-frequency detector and applying it to the charge pump circuit requires time. This time creates a dead zone in the entire phase-locked loop system and causes a jitter in the phase-locked loop. This paper solves this challenge by combining PFD and CP blocks. This structure's proposed design and simulation results show that the overall phase-locked loop system has a very low output jitter due to the significant reduction of the dead zone and the integration of the phase-frequency detector blocks and the charge pump. The simulations carried out in 90 nm CMOS technology indicate also a reduction in power consumption to 85 microwatts, a dead zone close to zero, and an operating frequency of 4.2 GHz, phase noise is -123dBc/Dec and the results of which have been compared with previous works. Monte-Carlo simulation from post-layout simulation is carried out and the result is that the average power consumption ranged from a minimum of 61.4 microwatts to a maximum of 101.6 microwatts, and the delay and PDP also changed from 36.6ps to 59.1ps and 3.22 to 4.23, respectively.

Keywords

  • Phase-Frequency detector,
  • Charge pump,
  • Dead Zone,
  • Jitter,
  • Power Consumption
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