10.57647/j.spre.2025.0903.16

Optimized Reversible Parity-Preserving Multiplier Circuits in Nanotechnology

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  • Meysam Mappar1,
  • Ehsan PourAliAkbar*2,
  • Amin MehranZadeh3,
  • Mohammad Mosleh3,
  1. Department of Computer Engineering, Dez.C., Islamic Azad University, Dezful, Iran
  2. Department of Computer Engineering, MaS.C., Islamic Azad University, Masjed Soleiman, Iran
  3. Department of Computer Engineering, Dez.C., Islamic Azad University, Dezful, Iran.

Received: 2025-06-18

Revised: 2025-07-21

Accepted: 2025-08-20

Published in Issue 2025-10-27

Copyright (c) 2025 Meysam Mappar, Ehsan PourAliAkbar, Amin MehranZadeh, Mohammad Mosleh (Author)

Creative Commons License

This work is licensed under a Creative Commons Attribution-NoDerivatives 4.0 International License.

How to Cite

Mappar, M., pouraliakbar, ehsan, MehranZadeh, A. ., & Mosleh, M. . (2025). Optimized Reversible Parity-Preserving Multiplier Circuits in Nanotechnology. Signal Processing and Renewable Energy (SPRE), 9(3 (September 2025). https://doi.org/10.57647/j.spre.2025.0903.16
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Abstract

Reversible logic, as one of the new technologies, plays a significant role in designing quantum computers due to the absence of energy loss, as well as using reversible circuits in low-power CMOS circuits, quantum calculations, and DNA computing. Multipliers are among the most critical circuits in computer calculations. This study proposes an optimized unsigned and signed reversible parity-preserving multiplier circuit. In addition, this study seeks to present a reversible block, as well as reversible signed and unsigned multiplier circuits using the presented block and the proposed design. The presented circuits reduce the quantum cost and are considered parity-preserving. In order to utilize the designs presented in variable sizes, two circuits in n×n sizes are provided. Further, a number of equations are presented to calculate the quantum costs, along with the number of constant inputs and garbage outputs in the proposed circuits.

Keywords

  • Quantum computing,
  • Signed multiplier,
  • Reversible multiplier,
  • Reversible logic,
  • Parity-preserving,
  • Unsigned multiplier
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