10.57647/j.spre.2025.0903.14

A 12 bit Non-Uniform Sampling SAR ADC Using Switchable Sampling Frequency

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  • Bahareh Shojaeirad1,
  • Amir Amirabadi*1,
  • Iman Ahanian1,
  1. Islamic Azad University

Received: 2025-05-06

Revised: 2025-08-18

Accepted: 2025-08-26

Published in Issue 2025-09-30

Copyright (c) 2025 Bahareh Shojaeirad, Amir Amirabadi, Iman Ahanian (Author)

Creative Commons License

This work is licensed under a Creative Commons Attribution-NoDerivatives 4.0 International License.

How to Cite

Shojaeirad, B., Amirabadi, A., & Ahanian, I. (2025). A 12 bit Non-Uniform Sampling SAR ADC Using Switchable Sampling Frequency. Signal Processing and Renewable Energy (SPRE), 9(3 (September 2025). https://doi.org/10.57647/j.spre.2025.0903.14
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Abstract

In this study, a frequency-division based successive approximation register analog-to-digital converter (SAR ADC) with two tone input signals and 12-bit resolution is developed in 0.18μm CMOS technology. The sampling frequency is 24 KHz. The base of this concept is non-uniform sampling achieved by phase/frequency detectors, frequency divider blocks, and up/down thermometer counter. In this design, the power consumption of the data converter is significantly lowered without sacrificing the linearity of the system by decreasing the sample frequency when the input signal will be slow down, such as biological signals that do not change frequently. At a 1.8 V supply, a factor of merit (FOM) of fJ/conversion 6.95 is attained.

Keywords

  • Analog-to-digital converter (ADC), Successive approximation register (SAR), non-uniform sampling, reduced frequency, and low power
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References

  1. Fateh S. Calibration techniques for digitally assisted nyquist-rate ADCs: ETH Zurich; 2016.
  2. https://doi.org/10.3929/ethz-a-010655420
  3. Lin J-Y, Hsieh C-C. A 0.3 V 10-bit 1.17 f SAR ADC with merge and split switching in 90 nm CMOS. IEEE Transactions on Circuits and Systems I: Regular Papers. 2014;62(1):70-9. https://doi.org/10.1109/TCSI.2014.2349571
  4. Lin Y-Z, Chang S-J, Shyu Y-T, Huang G-Y, Liu C-C, editors. A 0.9-V 11-bit 25-MS/s binary-search SAR ADC in 90-nm CMOS. IEEE Asian Solid-State Circuits Conference 2011; 2011: IEEE.
  5. https://doi.org/10.1109/ASSCC.2011.6123606
  6. Liu W, Huang P, Chiu Y. A 12-bit, 45-MS/s, 3-mW redundant successive-approximation-register analog-to-digital converter with digital calibration. IEEE Journal of Solid-State Circuits. 2011;46(11):2661-72.
  7. https://doi.org/10.1109/JSSC.2011.2163556
  8. Liu W, Huang P, Chiu Y, editors. A 12-bit 50-MS/s 3.3-mW SAR ADC with background digital calibration. Proceedings of the IEEE 2012 Custom Integrated Circuits Conference; 2012: IEEE.
  9. https://doi.org/10.1109/CICC.2012.6330694
  10. Tao Y, Lian Y. A 0.8-V, 1-MS/s, 10-bit SAR ADC for multi-channel neural recording. IEEE Transactions on Circuits and Systems I: Regular Papers. 2014;62(2):366-75.
  11. https://doi.org/10.1109/TCSI.2014.2360762
  12. Johns DA, Martin K. Analog integrated circuit design: John Wiley & Sons; 2008.
  13. Tang X, Liu J, Shen Y, Li S, Shen L, Sanyal A, et al. Low-power SAR ADC design: Overview and survey of state-of-the-art techniques. IEEE Transactions on Circuits and Systems I: Regular Papers. 2022;69(6):2249-62.
  14. https://doi.org/10.1109/TCSI.2022.3166792
  15. Schinkel D, Mensink E, Klumperink E, Van Tuijl E, Nauta B, editors. A double-tail latch-type voltage sense amplifier with 18ps setup+ hold time. 2007 IEEE international solid-state circuits conference Digest of technical papers; 2007: IEEE.
  16. https://doi.org/10.1109/ISSCC.2007.373420
  17. Liu M, Pelzers K, van Dommele R, van Roermund A, Harpe P. A106nW 10 b 80 kS/s SAR ADC with duty-cycled reference generation in 65 nm CMOS. IEEE Journal of Solid-State Circuits. 2016;51(10):2435-45.
  18. https://doi.org/10.1109/JSSC.2016.2587688
  19. Harpe P, Zhang Y, Dolmans G, Philips K, De Groot H, editors. A 7-to-10b 0-to-4MS/s flexible SAR ADC with 6.5-to-16fJ/conversion-step. 2012 IEEE International Solid-State Circuits Conference; 2012: IEEE.
  20. https://doi.org/10.1109/ISSCC.2012.6177096
  21. Chen L, Sanyal A, Ma J, Tang X, Sun N, editors. Comparator common-mode variation effects analysis and its application in SAR ADCs. 2016 IEEE International Symposium on Circuits and Systems (ISCAS); 2016: IEEE.
  22. https://doi.org/10.1109/ISCAS.2016.7538972
  23. SW MC. A 6b 600MS/s 5.3 mW Asynchronous ADC in 0.13 um CMOS. ISSCC Dig Tech Papers, Feb 2006. 2006:574-5.
  24. https://doi.org/10.1109/JSSC.2006.884231
  25. Donoho DL. Compressed sensing. IEEE Transactions on information theory. 2006;52(4):1289-306.
  26. https://doi.org/10.1109/TIT.2006.871582
  27. Anastasia BV, Mikhail PN, editors. An Analog-to-information Converter Using Non-Uniform Sampling Architecture and SAR ADC. 2022 Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus); 2022: IEEE.
  28. https://doi.org/10.1109/ElConRus54750.2022.9755580
  29. Fateh S, Schönle P, Bettini L, Rovere G, Benini L, Huang Q. A reconfigurable 5-to-14 bit SAR ADC for battery-powered medical instrumentation. IEEE Transactions on Circuits and Systems I: Regular Papers. 2015;62(11):2685-94.
  30. https://doi.org/10.1109/TCSI.2015.2477580
  31. Wannamaker RA, Lipshitz SP, Vanderkooy J, Wright JN. A theory of nonsubtractive dither. IEEE Transactions on Signal Processing. 2000;48(2):499-516.
  32. https://doi.org/10.1109/78.823976
  33. Harpe P, Cantatore E, Van Roermund A. A 10b/12b 40 kS/s SAR ADC with data-driven noise reduction achieving up to 10.1 b ENOB at 2.2 fJ/conversion-step. IEEE Journal of Solid-State Circuits. 2013;48(12):3011-8.
  34. https://doi.org/10.1109/JSSC.2013.2278471
  35. Silva VML, de Souza AAL, Catunda SYC, Freire RCS, editors. Non-uniform sampling based ADC architecture using an adaptive level-crossing technique. 2017 IEEE International Instrumentation and Measurement Technology Conference (I2MTC); 2017: IEEE.
  36. https://doi.org/10.1109/I2MTC.2017.7969771
  37. Wu T-F, Dey S, Chen MS-W. A nonuniform sampling ADC architecture with reconfigurable digital anti-aliasing filter. IEEE Transactions on Circuits and Systems I: Regular Papers. 2016;63(10):1639-51.
  38. https://doi.org/10.1109/TCSI.2016.2586523
  39. Zaare M, Sepehrian H, Maymandi-Nejad M. A new non-uniform adaptive-sampling successive approximation ADC for biomedical sparse signals. Analog Integrated Circuits and Signal Processing. 2013;74:317-30.
  40. http:// doi.org/10.1007/s10470-012-9984-7
  41. Maloberti F. Data converters specifications: Springer; 2007.
  42. https://doi.org/10.1007/978-0-387-32486-9_2
  43. Razavi B. Principles of data conversion system design. (No Title). 1994.
  44. https://doi.org/10.1109/9780470545638
  45. Song B-S. MicroCMOS design: CRC Press; 2011.
  46. https://doi.org/10.1201/b11192
  47. Liu C-C, Huang M-C, Tu Y-H. A 12 bit 100 MS/s SAR-assisted digital-slope ADC. IEEE Journal of Solid-State Circuits. 2016;51(12):2941-50.
  48. https://doi.org/10.1109/JSSC.2016.2591822
  49. Marvasti F. Nonuniform sampling: theory and practice: Springer Science & Business Media; 2012.
  50. https://doi.org/10.1007/978-1-4612-0143-4
  51. Hussein AI, Vasadi S, Paramesh J. A 450 fs 65-nm CMOS millimeter-wave time-to-digital converter using statistical element selection for all-digital PLLs. IEEE Journal of Solid-State Circuits. 2017;53(2):357-74.
  52. https://doi.org/10.1109/JSSC.2017.2762698
  53. Jeong G-S, Kim W, Park J, Kim T, Park H, Jeong D-K. A 0.015-mm2 Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology. IEEE Transactions on Circuits and Systems II: Express Briefs. 2015;64(6):655-9.
  54. https://doi.org/10.1109/TCSII.2015.2504274
  55. Kull L, Luu D, Menolfi C, Braendli M, Francese PA, Morf T, et al. A 24–72-GS/s 8-b time-interleaved SAR ADC with 2.0–3.3-pJ/conversion and> 30 dB SNDR at Nyquist in 14-nm CMOS FinFET. IEEE Journal of Solid-State Circuits. 2018;53(12):3508-16.
  56. https://doi.org/10.1109/JSSC.2018.2859757
  57. Lee J, Chiang P-C, Peng P-J, Chen L-Y, Weng C-C. Design of 56 Gb/s NRZ and PAM4 SerDes transceivers in CMOS technologies. IEEE Journal of Solid-State Circuits. 2015;50(9):2061-73.
  58. https://doi.org/10.1109/JSSC.2015.2433269
  59. Shu G, Choi W-S, Saxena S, Talegaonkar M, Anand T, Elkholy A, et al. A 4-to-10.5 Gb/s continuous-rate digital clock and data recovery with automatic frequency acquisition. IEEE Journal of Solid-State Circuits. 2015;51(2):428-39.
  60. https://doi.org/10.1109/JSSC.2015.2497963
  61. Miller R. Fractional-frequency generators utilizing regenerative modulation. Proceedings of the IRE. 1939;27(7):446-57.
  62. https://doi.org/10.1109/JRPROC.1939.228513
  63. Murata K, Otsuji T, Sano E, Ohhata M, Togashi M, Suzuki M. A novel high-speed latching operation flip-flop (HLO-FF) circuit and its application to a 19-Gb/s decision circuit using a 0.2-/spl mu/m GaAs MESFET. IEEE Journal of Solid-State Circuits. 1995;30(10):1101-8.
  64. https://doi.org/10.1109/4.466072
  65. Rategh HR, Lee TH. Superharmonic injection-locked frequency dividers. IEEE Journal of Solid-State Circuits. 1999;34(6):813-21.
  66. https://doi.org/10.1109/4.766815
  67. Razavi B. Design of integrated circuits for optical communications: John Wiley & Sons; 2012.
  68. Lee J, Razavi B. A 40-GHz frequency divider in 0.18-/spl mu/m CMOS technology. IEEE Journal of solid-state circuits. 2004;39(4):594-601.
  69. https://doi.org/10.1109/JSSC.2004.825119
  70. Heydari P, Mohanavelu R. A 40-GHz flip-flop-based frequency divider. IEEE Transactions on Circuits and Systems II: Express Briefs. 2006;53(12):1358-62.
  71. https://doi.org/10.1109/TCSII.2006.885393
  72. Feng C, Yu XP, Lim WM, Yeo KS. A 40 GHz 65 nm CMOS phase-locked loop with optimized shunt-peaked buffer. IEEE Microwave and Wireless Components Letters. 2014;25(1):34-6.
  73. https://doi.org/10.1109/LMWC.2014.2365994
  74. Razavi B. Design of analog CMOS integrated circuits: 清华大学出版社有限公司; 2005.
  75. Hyun Y, Park I-C. Constant-Time Synchronous Binary Counter With Minimal Clock Period. IEEE Transactions on Circuits and Systems II: Express Briefs. 2021;68(7):2645-9.
  76. https://doi.org/10.1109/TCSII.2021.3054014
  77. Shah OA, Vats S, editors. Floorplanning and Comparative Analysis of 16-bit Synchronous Up/Down Counter in Different CMOS Technology. 2023 International Conference on Computational Intelligence and Sustainable Engineering Solutions (CISES); 2023: IEEE.
  78. https://doi.org/10.1109/CISES58720.2023.10183608
  79. Luo Y, Jain A, Wagner J, Ortmanns M. Input referred comparator noise in SAR ADCs. IEEE Transactions on Circuits and Systems II: Express Briefs. 2019;66(5):718-22.
  80. https://doi.org/10.1109/TCSII.2019.2909429
  81. Ding M, Harpe P, Liu Y-H, Busze B, Philips K, de Groot H, editors. 26.2 A 5.5 fJ/conv-step 6.4 MS/S 13b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme. 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of Technical Papers; 2015: IEEE.
  82. https://doi.org/10.1109/ISSCC.2015.7063125