Novel robust quantum-dot cellular automata (QCA) full adder in the one-dimensional clock

Authors

• Milad Ebrahimy ¹
• Mohammad Gholami * ²
• Habib Adarang ¹
• Reza Yosefi ¹

1. Department of Electrical Engineering, Nour Branch, Islamic Azad University, Nour, Iran.
2. Department of Electrical Engineering, Faculty of Engineering and Technology, University of Mazandaran, Babolsar, Iran.

Abstract

Quantum-dot cellular automata technology has emerged as an alternative for complementary metal oxide semiconductor  technology in very-large-scale integration (VLSI) circuits. The basis and structure of QCA technology are different from CMOS technology, and it is necessary to redesign the existing circuits based on the characteristics of QCA technology. In this paper, first, five-input and three-input majority gates are proposed with the ability to work in the one-dimensional clock. Then a full adder based on the proposed majority gates in the one-dimensional clock was designed with 0.75 clock cycle latency. As a consequence of the location of the circuit’s inputs & outputs, this full adder can easily be converted to a multi-bit adder. This paper introduces a four-bit adder utilizing the same method, endeavoring to design the circuit compliant with the inherent features of QCA technology and prove that the proposed circuit can be constructed. For design as well as manufacturing process simplicity, a general framework for design (in one-dimensional clock) is also hereby proposed. Proposed designs are confirmed by QCADesigner, a well-known QCA layout design and verification tool, and QCADesigner-E for power analysis.

Graphical Abstract

Keywords

• Majority
• QCA
• 1-d Clocking
• QCADesigner E
• RCA Adder
• Full adder
• Five-Input Majority Gate

References

[1] Majeed A. H., Alkaldy E., Bin Zainal M. S., Bin D., (2019), A new 5-input majority gate without adjacent inputs crosstalk effect in QCA technology. Indones. J. Electric. Eng. Comput. Sci. 14: 1159–1164.
[2] Mo L., Lent C. S., (2005), Power dissipation in clocked quantum-dot cellular automata circuits. Device Res. Conf. Digest. DRC. 2005(1993), 123–124.
[3] Vacca M., Vighetti D., Mascarino M., Amaru L. G., Graziano M., Zamboni M., (2011), Magnetic QCA majority voter feasibility analysis. 2011 7th Conf. on Ph.D. Res. Microelect. Electron. PRIME. Conf. Proc. 229–232.
[4] Purkayastha T., De D., Das B., Chattapadhyay T., (2016), First principle study of molecular quantum dot cellular automata using mixed valence compounds. 2016 3rd Int. Conf. Dev. Circ. Sys. (ICDCS). 244–248.
[5] Cho H., Swartzlander E. E., (2009), Adder and multiplier design in quantum-dot cellular automata. IEEE Transact. Comput. 58: 721–727.
[6] Raj M., Gopalakrishnan L., Ko S. B., (2021), Design and analysis of novel QCA full adder-subtractor. Int. J. Elect. Lett. 9: 287–300.
[7] Seyedi S., Navimipour N. J., (2018), An optimized design of full adder based on nanoscale quantum-dot cellular automata. Optik. 158: 243–256.
[8] Vahabi M., Lyakhov P., Bahar A. N., (2021), Design and implementation of novel efficient full adder/subtractor circuits based on quantum-dot cellular automata technology. Appl. Sci. 11: 8717-8721.
[9] Mousavi H. A., Keshavarzian P., Molahosseini A. S., (2020), A novel fast and small XOR-base full-adder in quantum-dot cellular automata. Appl. Nanosc. (Switzerland). 10: 4037–4048.
[10] Hashemi S., Tehrani M., Navi K., (2012), An efficient quantum-dot cellular automata full-adder. Scientif. Res. Essays. 7: 177–189.
[11] Abdullah-Al-Shafi M., Bahar A. N., (2018), An architecture of 2-dimensional 4-dot 2-electron QCA full adder and subtractor with energy dissipation study. Active and Passive Electron. Compon. 2018. Article ID 5062960.
[12] Singh S., (2019), An optimized approach towards reversible adder / subtractor design on QCA. I. J. Modern Educ. Comp. Sci. 10: 47–53.
[13] Kalpana K., Paulchamy B., Chinnapparaj S., Mahendrakan K., Abdulhayum A., (2021), A novel design of nano scale TIEO based single layer full adder and full subractor in QCA paradigm. Proceedings - 5th Int. Conf. on Intelligent Comput. Cont. Sys. ICICCS 2021, Iciccs. 575–582.
[14] Mandai N. K., Chakrabarty R., (2017), Complementary dual-output universal gate in quantum dot cellular automata. 2017 8th Annual Indus. Automat. Electromechan. Eng. Conf. (IEMECON). 321–323.
[15] Rani S., Sasamal T. N., (2018), Design of QCA circuits using new 1D clocking scheme. 2nd Int. Conf. Telecommunic. Networks. TEL-NET . 1–6.
[16] Goswami M., Mondal A., Mahalat M. H., Sen B., Sikdar B. K., (2020), An efficient clocking scheme for quantum-dot cellular automata. Int. J. Electron. Lett. 8: 83–96.
[17] Bahar A. N., Waheed S., (2016), Design and implementation of an efficient single layer five input majority voter gate in quantum-dot cellular automata. Springer Plus. 2016: Article Number: 636.
[18] Cocorullo G., Corsonello P., Frustaci F., Perri S., (2017), Design of efficient BCD adders in quantum-dot cellular automata. IEEE Transact. Circuits and Systems II: Express Briefs 64: 575–579.
[19] Walus K., Dysart T. J., Jullien G. A., Budiman R. A., (2004), QCADesigner: A rapid design and simulation tool for quantum-dot cellular automata. Nanotechnol: IEEE Transact. On. 3: 26–31.
[20] Srivastava S., Asthana A., Bhanja S., Sarkar S., (2011), QCAPro -An error-power estimation tool for QCA circuit design. 2011 IEEE Int. Symp. Circuits Sys. (ISCAS). 2377–2380.
[21] Torres F. S., Wille R., Niemann P., Drechsler R., (2018), An energy-aware model for the logic synthesis of quantum-dot cellular automata. IEEE Transact. Comp.-Aided Design of Integ. Circuits and Sys. 37: 3031–3041.
[22] Kumar P., Singh S., (2019), Optimization of the area efficiency and robustness of a QCA-based reversible full adder. J. Comput. Electron. 18: 1478–1489.
[23] Gudivada A. A., Sudha G. F., (2020), Design of baugh–wooley multiplier in quantum-dot cellular automata using a novel 1-bit full adder with power dissipation analysis. SN Appl. Sci. 2: 1–13.
[24] Heikalabad S. R., Asfestani M. N., Hosseinzadeh M., (2018), A full adder structure without cross-wiring in quantum-dot cellular automata with energy dissipation analysis. J. Supercomp. 74: 1994–2005.
[25] Abedi D., Jaberipur G., Sangsefidi M., (2015), Coplanar full adder in quantum-dot cellular automata via clock-zone-based crossover. IEEE Transact. Nanotechnol. 14: 497–504.
[26] Angizi S., Alkaldy E., Bagherzadeh N., Navi K., (2014), Novel robust single layer wire crossing approach for exclusive or sum of products logic design with quantum-dot cellular automata. J. Low Power Elect. 10: 259–271.
[27] Faraji H., Mosleh M., (2018), A fast wallace-based parallel multiplier in quantum-dot cellular automata. Int. J. Nano Dimens. 9: 68-78.
[28] Balali M., Rezai A., Balali H., Rabiei F., Emadi S., (2017a), Towards coplanar quantum-dot cellular automata adders based on efficient three-input XOR gate. Results in Physics. 7: 1389–1395.
[29] Bhoi B. K., Misra N. K., Pradhan M., (2018), A novel vedic divider based crypto-hardware for nanocomputing paradigm: An extended perspective. Int. J. Nano Dimens. 9: 336–345.
[30] Pudi V., Sridharan K., (2012), Low complexity design of ripple carry and brent–kung adders in QCA. IEEE Transact. Nanotechnol. 11: 105–119.
[31] Roshany H. R., Rezai A., (2019), Novel efficient circuit design for multilayer QCA RCA. Int. J. Theoret. Phys. 58: 1745–1757.
[32] Kumawat R., Sasamal T. N., (2016), Design of 1-bit and 4-bit adder using reversible logic in quantum-dot cellular automata. 2016 IEEE Int. Conf. Recent Trends in Electron. Inf. Communic. Technol. (RTEICT). 593–597.
[33] Mohammadi M., Mohammadi M., Gorgin S., (2016), An efficient design of full adder in quantum-dot cellular automata (QCA) technology. Microelect. J. 50: 35–43.