10.57647/ijnd.2026.1703.08

Enhanced Electrostatic Control and Biosensing in a No Junction Gate all Around Hetero Dielectric Tunnel Field Effect Transistor (NJGAA-HTFET): A Nanoscale Study Through Analytical Modeling and TCAD Simulation

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  • Vimala Palanichamy*1,
  • Sharon Geege Augustine2,
  • Arun Samuel Thankamony Sarasam2,
  • Suveetha Dhanaselvam3,
  • Jayagowri Ramamoorthy4,
  1. Department of ECE, Dayananda Sagar College of Engineering, Bengaluru, India
  2. Department of ECE, National Engineering College, Tamilnadu, India
  3. Department of ECE, Velammal College of Engineering & Technology, Madurai, India
  4. Department of ECE, BMS College of Engineering, Karnataka, Bengaluru, India

Received: 2025-12-15

Revised: 2026-01-16

Accepted: 2026-02-24

Published Online: 2026-04-27

Copyright (c) 2026 Vimala Palanichamy, Sharon Geege Augustine, Arun Samuel Thankamony Sarasam, Suveetha Dhanaselvam, Jayagowri Ramamoorthy (Author)

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

Palanichamy, V., Augustine, S. G., Sarasam, A. S. T., Dhanaselvam, S., & Ramamoorthy, J. (2025). Enhanced Electrostatic Control and Biosensing in a No Junction Gate all Around Hetero Dielectric Tunnel Field Effect Transistor (NJGAA-HTFET): A Nanoscale Study Through Analytical Modeling and TCAD Simulation. International Journal of Nano Dimension, 17(2 (April 2026). https://doi.org/10.57647/ijnd.2026.1703.08
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Abstract

In the modern era of miniaturization, Tunnel Field Effect Transistor (TFET) is considered to be a dominant device for low-power applications due to its primary switching mechanism. The concept of TFETs is that quantum tunnelling across a barrier is regulated, whereas in conventional MOSFETs, the thermionic emission across a barrier is regulated. In this paper, the No Junction Gate All Around Hetero Dielectric Tunnel Field Effect Transistor (NJGAA-HTFET) is modelled at large drain voltage, even though the effect of drain voltages is less pronounced. Theoretical tests have proved that using the low-voltage TFETs in logic circuits instead of MOSFETs, will conserve significant amounts of electricity. Hence, this work presents the analytical modelling of the No Junction Gate All Around Hetero Dielectric Tunnel Field Effect Transistor, where surface potential profile, IDS VGS, and IDS VDS characteristics are analytically modelled using the Kane approach. A comparison of TCAD simulation and modeling under various device parameters, including gate oxide dielectric constant, channel lengths, and junction/junctionless structures, is conducted and further discussed to validate the model. The results of the Ion/Ioff ratio of the proposed device prove to be superior to those of conventional JLTFET devices. More specifically, the NJGAA-HDTFET is identified for use as a biosensor to detect various biomolecules.

Keywords

  • TFET,
  • Nanometer,
  • No junction,
  • Gate all around,
  • TCAD,
  • Analytical model,
  • Parabolic approximation
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References

  1. Kuhn K. J., (2011), The ultimate CMOS device scaling limits. Proc. Int. Symp. VLSI Technol. Syst. Appl., Hsinchu, Taiwan, 1–2.
  2. Shree G. N., Priyadarshini U., Keerthana M., Vimala P., (2020), Proc. Int. Conf. Emerg. Trends Inf. Technol. Eng. (ic-ETITE), Vellore, India, 1–5.
  3. Vimala P., Kumar N. R. N., (2020), Quantum Modelling of Nanoscale Silicon Gate-All-Around Field Effect Transistor. J. Nano Res., 64: 115–122.
  4. Usha C., Vimala P., (2020), Analytical drain current modelling and simulation of triple material gate-all-around heterojunction TFETs considering depletion regions. Semiconductors, 54: 1634–1640.
  5. Vimala P., Samuel T. S. A., (2019), A Simulation Study on the Impact of InP Barrier on InGaAs/InP Hetero Junction Gate all around MOSFET. J. Nano Res., 60: 113–123.
  6. Vimala P., (2018), Charge-based quantization model for triple-gate FinFETs. J. Nano Electron. Phys., 10(5): 05015 (5 pp).
  7. Jamali, M., Hajialigol, N., (2025), Optimizing thermal efficiency: A Study on parabolic trough solar collector performance with nanofluids and fin designs. Int. J. Nano Dimens. https://doi.org/10.57647/j.ijnd.2025.1604.31
  8. Purwar, V. (2024). High-K dual metal gate-nano tube (DMG-NT) field effect transistors (FETs): A possible solution to diminish the effect of temperature variation. International Journal of Nano Dimension, 15(4 (October 2024). https://doi.org/10.57647/j.ijnd.2024.1504.31
  9. Babak Sadeghi, R.A.R. Vahdati, (2012). Comparison and SEM-characterization of novel solvents of DNA/carbon nanotube, Applied Surface Science, Volume 258, Issue 7. https://doi.org/10.1016/j.apsusc.2011.11.042.
  10. Vimala P., SS S., Krishna L., Bassapuri M., Manikanta T., (2020), Proc. IEEE Int. Conf. Electron. Comput. Commun. Technol. (CONECCT), Bangalore, India, 1–4.
  11. Mori T., Iizuka S., Nakayama T., (2017), Material engineering for silicon tunnel field-effect transistors: isoelectronic trap technology. MRS Commun., 7: 541–550.
  12. Vimala P., Krishna L., Maheshwari K., Sharma S. S., (2020), J. Nano Electron. Phys., 12(5): 05027 (5 pp).
  13. Saleem S., Vimala P., (2022), Proc. Int. Conf. Appl. Artif. Intell. Comput. (ICAAIC), Salem, India, 1–4.
  14. Vimala P., Bassapuri M., Harshavardhan C. R., Maheswari K., Harshith P., Raikar N. N., (2021), Proc. IEEE Int. Conf. Electron. Comput. Commun. Technol. (CONECCT), Bangalore, India, 1–5.
  15. Xie H., Liu H., Wang S., Chen S., Han T., Li W., (2020), Improvement of Electrical Performance in Heterostructure Junctionless TFET Based on Dual Material Gate. Appl. Sci., 10(1): 126.
  16. Vimala P., Balamurugan N. B., (2013), Analytical modeling of quantization effects in surrounding-gate MOSFETs. COMPEL – Int. J. Comput. Math. Electr. Electron. Eng., 33(1–2): 630–644.
  17. Abdulnassir R., Singh A., Tekilu D., et al., (2024), Assessment of hetero-structure junction-less tunnel FET’s efficacy for biosensing applications. Sens. Imaging, 25: 6.
  18. Rajabi B., Vadizadeh M., Sedigh Ziabari S. A., (2025), Digital and analog performance enhancement of nanotube heterojunctionless tunnel FET using core-shell gate technology. Int. J. Nano Dimens., 16(2)