In this paper a new implementation of CMOS ripple comparator cell using the Gate-Diffusion Input (GDI) technique is presented. The proposed design using this technique allows for the reduction of power consumption, propagation delay, and the area of digital circuits while maintaining low complexity of logical design. The performance comparison with standard CMOS and GDI […]
In this paper, an optical communication receiver system for 5Gbps applications is proposed concerning power consumption. An inductor-less circuit in three-stages is proposed as the trans-impedance amplifier (TIA), which benefits from the inherent low input resistance of a common gate topology as the first stage. By forming two zeros in this TIA, proper frequency response […]
An optical communication receiver system is presented in this research using 65nm CMOS, which consists of three low-power active differential stages as Limiting Amplifier (LA) following an ultra-low-power RGC-Based Transimpedance Amplifier (RB-TIA). The presented active circuit of the RB-TIA is followed by a gain stage that extends the -3dB frequency of the circuit by creating […]
In this paper, the design methodology for a high-speed 8B/10B encoding architecture has been discussed. By means of the new truth table and with the help of Pass-Transistor Logic (PTL), a new structure has been designed in CMOS technology, which shows a superior speed performance. Also, power consumption is optimized because of careful design considerations. […]
This paper presents a broadband low-power CMOS low noise amplifier (LNA) in 130 nm technology for sub-GHz Internet of Things (IoT) applications. The proposed circuit consists of a current reuse common source amplifier (CSA) in the forward path, and a positive simple transconductance amplifier (PSTA) in the feedback path. Theoretical calculation of the input admittance […]
In this paper, a new hybrid low-power and area efficient Carry Look-Ahead Adder in CNFET technology based on the full-swing Gate Diffusion Input (GDI) technique is proposed. The proposed CLA design in GDI logic style, not only decreases the circuit area effectively but also decreases the power consumption and delay parameters as well. The proposed […]
