This review paper contains the discussion about performance analysis of high speed 4-2 compressor architectures, starting from the general idea; conventional form for implementation of this building block along with its truth table has been studied. Thereafter, the modified versions which show promise for high speed multiplier implementations along with their benefits and drawbacks were […]
In this article, the design procedure of a low latency Booth multiplier has been proposed. With the help of a novel 4-2 compressor, a high-performance 16×16 bit Booth multiplier has been implemented, which depicts high operating frequency. To achieve this, the proposed 4-2 compressor has been utilized successively in the Partial Product Reduction Tree (PPRT) […]
