This review paper contains the discussion about performance analysis of high speed 4-2 compressor architectures, starting from the general idea; conventional form for implementation of this building block along with its truth table has been studied. Thereafter, the modified versions which show promise for high speed multiplier implementations along with their benefits and drawbacks were […]
In this paper, the design methodology for a high-speed 8B/10B encoding architecture has been discussed. By means of the new truth table and with the help of Pass-Transistor Logic (PTL), a new structure has been designed in CMOS technology, which shows a superior speed performance. Also, power consumption is optimized because of careful design considerations. […]
