A complimentary topology is used incorporating TSMC 0.18 mm process to design a CMOS VCO with the center frequency of 5.4 GHz. Simulation results showed tuning range of 13%. The phase noise at 1 MHz offset was measured to be -118.7 dBc/Hz. The VCO core power consumption was 3.3 mW when the power supply voltage […]
In this paper, a CMOS four quadrant multiplier based on flipped voltage follower and differential squaring circuit is presented. The proposed circuit has a compact architecture operating at a higher speed and a higher input voltage range compared to the previously presented structures. The transistors operate in the both saturation and ohmic regions. The circuit […]
Design of a very compact two stage amplifier is proposed by merging passive frequency compensation with a feed forward compensation technique, which achieves significant improvement in gain-bandwidth product (GBW), slew rate and phase margin with lower supply voltage requirement. The mathematical analysis given in this paper justify that the proposed technique offers the advantage of […]
In this paper, the design methodology for a high-speed 8B/10B encoding architecture has been discussed. By means of the new truth table and with the help of Pass-Transistor Logic (PTL), a new structure has been designed in CMOS technology, which shows a superior speed performance. Also, power consumption is optimized because of careful design considerations. […]
