Published in Issue 2018-09-28
How to Cite
Abedini, M., Sedigh Ziabari, S. A., & Eskandarian, A. (2018). Representation of heterostructure electrically doped nanoscale tunnel FET with Gaussian-doping profile for high-performance low-power applications. International Nano Letters, 8(4 (December 2018). https://doi.org/10.1007/s40089-018-0250-6
HTML views: 38
PDF views: 109
Abstract
Abstract In this paper, a gallium antimonide junctionless tunnel field-effect transistor based on electrically doped concept (GaSb–EDTFET) is studied and simulated. The performance of the device is analyzed based on the energy band diagram and electric field profile. The on-current, transconductance, and cut-off frequency are enhanced in case of GaSb–EDTFET compared with Si-EDTFET due to the combination of the high tunneling efficiency of the narrow bandgap and the high-electron mobility of GaSb. On the other hand, the Gaussian-doping profile decreases the ambipolar and off current by increasing the tunneling barrier length at the drain/channel interface. Hence, applying Gaussian-doping profile on GaSb–EDTFET makes it a suitable candidate for analog and digital applications. Next, heterostructure channel/source interface EDTFET is studied which uses GaSb for the source and AlGaSb for the drain and channel regions. Then, it has been optimized by numerical simulation in terms of aluminum (Al) composition. The optimal Al composition was founded to be around 10% ( x = 0.1). It is shown that the blend of Gaussian-doping profile and the heterostructure channel/source interface with optimal Al composition remarkably reduces ambipolar current amount to a value of 1.3 × 10 −23 A/μm. The improvements in terms of I off , I on , I on / I off rate, subthreshold swing, transconductance, cut-off frequency, and also suppressed ambipolar behavior are illustrated by numerical simulations.Keywords
- Electrically doped tunnel field-effect transistor,
- Ambipolar current,
- Gaussian doping,
- Heterostructure
References
- Boucart and Ionescu (2007) Double-gate tunnel FET with high-k gate dielectric 54(7) (pp. 1725-1733) https://doi.org/10.1109/TED.2007.899389
- Pal and Dutta (2016) Analytical drain current modeling of double-gate tunnel field-effect transistors 63(8) (pp. 3213-3221) https://doi.org/10.1109/TED.2016.2581842
- Ionescu and Riel (2011) Tunnel field-effect transistors as energy-efficient electronic switches 479(7373) (pp. 329-338) https://doi.org/10.1038/nature10679
- Colinge (2008) Springer https://doi.org/10.1007/978-0-387-71752-4
- Kim et al. (2014) High performance tri-gate extremely thin-body InAs-on-insulator MOSFETs with high short channel effect immunity and Vth tunability 61(5) (pp. 1354-1360) https://doi.org/10.1109/TED.2014.2312546
- Sharma and Vishvakarma (2013) Precise analytical model for short-channel quadruple-gate gate-all-around MOSFET 12(3) (pp. 378-385) https://doi.org/10.1109/TNANO.2013.2251895
- Colinge et al. (2010) Nanowire transistors without junctions 5(3) (pp. 225-229) https://doi.org/10.1038/nnano.2010.15
- Bhuwalka et al. (2005) Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering 52(5) (pp. 909-917) https://doi.org/10.1109/TED.2005.846318
- Nirschl et al. (2006) Scaling properties of the tunneling field effect transistor (TFET): device and circuit 50(1) (pp. 44-51) https://doi.org/10.1016/j.sse.2005.10.045
- Zhang et al. (2006) Low-subthreshold-swing tunnel transistors 27(4) (pp. 297-300) https://doi.org/10.1109/LED.2006.871855
- Wang et al. (2004) Complementary tunneling transistor for low power application 48(12) (pp. 2281-2286) https://doi.org/10.1016/j.sse.2004.04.006
- Choi et al. (2007) Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec 28(8) (pp. 743-745) https://doi.org/10.1109/LED.2007.901273
- Kao et al. (2012) Direct and indirect band-to-band tunneling in germanium-based TFETs 59(2) (pp. 292-301) https://doi.org/10.1109/TED.2011.2175228
- Yadav et al. (2016) Impactful study of dual work function, underlap and hetero gate dielectric on TFET with different drain doping profile for high frequency performance estimation and optimization (pp. 36-46) https://doi.org/10.1016/j.spmi.2016.04.027
- Rahi et al. (2017) Heterogate junctionless tunnel field-effect transistor: future of low-power devices 16(1) (pp. 30-38) https://doi.org/10.1007/s10825-016-0936-9
- Abdi and Kumar (2014) Controlling ambipolar current in tunneling FETs using overlapping gate-on-drain 2(6) (pp. 187-190) https://doi.org/10.1109/JEDS.2014.2327626
- Vladimirescu et al. (2012) An analysis on the ambipolar current in Si double-gate tunnel FETs (pp. 67-72) https://doi.org/10.1016/j.sse.2011.11.009
- Nigam and Sharma (2016) Approach for ambipolar behaviour suppression in tunnel FET by workfunction engineering 11(8) (pp. 460-464) https://doi.org/10.1049/mnl.2016.0178
- Madan and Chaujar (2017) Gate drain underlapped-PNIN-GAA-TFET for comprehensively upgraded analog/RF performance (pp. 17-26) https://doi.org/10.1016/j.spmi.2016.12.034
- Ilatikhameneh et al. (2015) Dielectric engineered tunnel field-effect transistor 36(10) (pp. 1097-1100) https://doi.org/10.1109/LED.2015.2474147
- Vijayvargiya and Vishvakarma (2014) Effect of drain doping profile on double-gate tunnel field-effect transistor and its influence on device RF performance (pp. 974-981) https://doi.org/10.1109/TNANO.2014.2336812
- Raad et al. (2016) Dielectric and work function engineered TFET for ambipolar suppression and RF performance enhancement 52(9) (pp. 770-772) https://doi.org/10.1049/el.2015.4348
- Ghosh et al. (2013) A junctionless tunnel field effect transistor with low subthreshold slope 12(3) (pp. 428-436) https://doi.org/10.1007/s10825-013-0450-2
- Goswami et al. (2014) Analog performance of Si junctionless tunnel field effect transistor and its improvisation using III–V semiconductor 4(21) (pp. 10761-10765) https://doi.org/10.1039/c3ra46535g
- Ghosh and Akram (2013) Junctionless tunnel field effect transistor 34(5) (pp. 584-586) https://doi.org/10.1109/LED.2013.2253752
- Anand et al. (2016) Performance analysis of charge plasma based dual electrode tunnel FET 37(5) https://doi.org/10.1088/1674-4926/37/5/054003
- Rahi and Ghosh (2015) High-k double gate junctionless tunnel FET with a tunable bandgap 5(67) (pp. 54544-54550) https://doi.org/10.1039/C5RA06954H
- Nigam et al. (2017) A barrier controlled charge plasma-based TFET with gate engineering for ambipolar suppression and RF/linearity performance improvement 64(6) (pp. 2751-2757) https://doi.org/10.1109/TED.2017.2693679
- Akram et al. (2014) P-type double gate junctionless tunnel field effect transistor 35(1) https://doi.org/10.1088/1674-4926/35/1/014002
- Nigam et al. (2017) Performance estimation of polarity controlled electrostatically doped tunnel field-effect transistor 12(4) (pp. 239-244) https://doi.org/10.1049/mnl.2016.0729
- Nigam et al. (2016) A new approach for design and investigation of junction-less tunnel FET using electrically doped mechanism (pp. 1-7) https://doi.org/10.1016/j.spmi.2016.07.016
- Lahgere et al. (2015) Electrically doped dynamically configurable field-effect transistor for low-power and high-performance applications 51(16) (pp. 1284-1286) https://doi.org/10.1049/el.2015.0079
- Anand and Sarin (2016) Analog and RF performance of doping-less tunnel FETs with Si0.55Ge0.45 source 15(3) (pp. 850-856) https://doi.org/10.1007/s10825-016-0859-5
- Kumar and Janardhanan (2013) Doping-less tunnel field effect transistor: design and investigation 60(10) (pp. 3285-3290) https://doi.org/10.1109/TED.2013.2276888
- Cecil and Singh (2017) Influence of Germanium source on dopingless tunnel-FET for improved analog/RF performance (pp. 244-252) https://doi.org/10.1016/j.spmi.2016.11.039
- Thathachary et al. (2014) Electron transport in multigate Inx Ga1–xAs nanowire FETs: from diffusive to ballistic regimes at room temperature 14(2) (pp. 626-633) https://doi.org/10.1021/nl4038399
- Lahgere et al. (2016) Dopingless ferroelectric tunnel FET architecture for the improvement of performance of dopingless n-channel tunnel FETs (pp. 16-25) https://doi.org/10.1016/j.spmi.2016.05.004
- Abadi and Ziabari (2016) Representation of type I heterostructure junctionless tunnel field effect transistor for high-performance logic application 122(6) https://doi.org/10.1007/s00339-016-0151-3
- Rahi et al. (2015) Temperature effect on hetero structure junctionless tunnel FET 36(3) https://doi.org/10.1088/1674-4926/36/3/034002
- Asthana et al. (2015) Improved performance of a junctionless tunnel field effect transistor with a Si and SiGe heterostructure for ultra low power applications 5(60) (pp. 48779-48785) https://doi.org/10.1039/C5RA03301B
- Gundapaneni et al. (2014) Improved Performance of Junctionless Tunnel FETs with Source/Channel Heterostructure (pp. 289-290) Springer International Publishing https://doi.org/10.1007/978-3-319-03002-9_73
- Cecil, K., Singh, J.: Performance enhancement of dopingless tunnel-FET based on Ge-source with high-k. IEEE International Symposium on Nanoelectronic and Information Systems, pp.19–22 (2015)
- Tirkey et al. (2017) Investigation of gate material engineering in junctionless TFET to overcome the trade-off between ambipolarity and RF/linearity metrics (pp. 307-315) https://doi.org/10.1016/j.spmi.2017.03.059
- Abadi and Ziabari (2016) Improved performance of nanoscale junctionless tunnel field-effect transistor based on gate engineering approach 122(11) https://doi.org/10.1007/s00339-016-0530-9
- Bal et al. (2014) Dual material gate junctionless tunnel field effect transistor 13(1) (pp. 230-234) https://doi.org/10.1007/s10825-013-0505-4
- Bashir et al. (2015) A high performance gate engineered charge plasma based tunnel field effect transistor 14(2) (pp. 477-485) https://doi.org/10.1007/s10825-015-0665-5
- Rahimian and Fathipour (2017) Improvement of electrical performance in junctionless nanowire TFET using hetero-gate-dielectric (pp. 142-152) https://doi.org/10.1016/j.mssp.2016.12.011
- Anand and Sarin (2017) Dual material gate doping-less tunnel FET with hetero gate dielectric for enhancement of analog/RF performance 38(2) https://doi.org/10.1088/1674-4926/38/2/024001
- Raad et al. (2016) Performance investigation of bandgap, gate material work function and gate dielectric engineered TFET with device reliability improvement (pp. 138-146) https://doi.org/10.1016/j.spmi.2016.04.016
- Ram and Abdi (2015) Dopingless PNPN tunnel FET with improved performance: design and analysis (pp. 430-437) https://doi.org/10.1016/j.spmi.2015.02.024
- Goswami et al. (2015) Junctionless tunnel field effect transistor with nonuniform doping 14(03) https://doi.org/10.1142/S0219581X14500252
- Aghandeh and Ziabari (2017) Gate engineered heterostructure junctionless TFET with Gaussian doping profile for ambipolar suppression and electrical performance improvement (pp. 103-114) https://doi.org/10.1016/j.spmi.2017.06.018
- Ahish et al. (2016) Device and circuit level performance analysis of novel InAs/Si heterojunction double gate tunnel field effect transistor (pp. 119-130) https://doi.org/10.1016/j.spmi.2016.04.008
- Visciarelli et al. (2016) Impact of strain on tunneling current and threshold voltage in III–V nanowire TFETs 37(5) (pp. 560-563) https://doi.org/10.1109/LED.2016.2539389
- Abadi and Ziabari (2016) Representation of strained gate-all-around junctionless tunneling nanowire filed effect transistor for analog applications (pp. 12-16) https://doi.org/10.1016/j.mee.2016.04.016
- Yadav et al. (2017) Comparative investigation of novel hetero gate dielectric and drain engineered charge plasma TFET for improved DC and RF performance (pp. 123-133) https://doi.org/10.1016/j.spmi.2017.06.016
- Yadav et al. (2016) A novel gate and drain engineered charge plasma tunnel field-effect transistor for low sub-threshold swing and ambipolar nature 100(266) (pp. 266-273) https://doi.org/10.1016/j.spmi.2016.09.029
- Yogesh et al. (2017) Nanoscale III–V on Si-based junctionless tunnel transistor for EHF band applications 38(5)
- Chin (1995) Electron mobility in GaSb 38(1) (pp. 59-67) https://doi.org/10.1016/0038-1101(94)E0063-K
- Unknown (2017) Silvaco Inc.
- Sze, S.M., Ng, K.K.: Physics of Semiconductor Devices. Wiley (2007)
- Asthana et al. (2014) Optimal design for a high performance H-JLTFET using hfo2 as a gate dielectric for ultra low power applications 4(43) (pp. 22803-22807) https://doi.org/10.1039/C4RA00538D
10.1007/s40089-018-0250-6