Improvement of digital and analog/RF performances of stacked gate oxide JLTFET using heterostructure and lightly doped drain
- Department of Electrical Engineering, Lan.C., Islamic Azad University, Langarud, Iran
Received: 2024-12-16
Revised: 2025-01-18
Accepted: 2025-01-20
Published in Issue 2025-06-01

This work is licensed under a Creative Commons Attribution 4.0 International License.
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Abstract
In this paper, a novel heterostructure stacked gate oxide junctionless tunnel field effect transistor (HS-SGO-JLTFET) with a lightly doped drain (LDD) region is proposed. The low band gap material (InAs) in the source region generates a stronger electric field in the source-channel junction, thereby increasing the ON current to 1.8×10-4 A/µm. Conversely, the lightly doped drain region near the channel end mitigates the electric field in the channel-drain junction, reducing the ambipolar current to 1.26×10-15 A/µm. Furthermore, the performance of the proposed device is analyzed with respect to analog/RF parameters. In this regard, the LDD-HS-SGO-JLTFET exhibits a smaller gate-to-drain capacitance (Cgd) of 0.14 fF, a larger transconductance (gm) of 840 µs, a higher cutoff frequency (fT) of 271 GHz, a bigger gain bandwidth product (GBWP) of 112 GHz, and a lower transit time ( ) of 6.55×10-13 s compared to the SGO-JLTFET. These improvements demonstrate that the proposed device is highly suitable for low-power and high-frequency applications.
Keywords
- Ambipolar Current,
- Heterostructure,
- Junctionless Tunnel Field Effect Transistor,
- Lightly Doped Drain,
- ON Current,
- Stacked Gate Oxide
References
- Ajayan J., Nirmal D., Tayal, S., Bhattacharya S., Arivazhagan L., Fletcher A., Murugapandiyan P., Ajitha D., (2021), Nanosheet field effect transistors-A next generation device to keep Moore's law alive: An intensive study. Microelectronics Journal. 114:105141. https://doi.org/10.1016/j.mejo.2021.105141
- Vashishtha V., Clark L. T., (2021), Comparing bulk-Si FinFET and gate-all-around FETs for the 5 nm technology node. Microelectronics Journal, 107: 104942. https://doi.org/10.1016/j.mejo.2020.104942
- Koswatta S. O., Lundstrom M. S., Nikonov D. E., (2009), Performance comparison between pin tunneling transistors and conventional MOSFETs. IEEE Trans Electron Devices. 56(3):456-465. https://doi.org/10.1109/TED.2008.2011934
- Lu H., Seabaugh A., (2014), Tunnel field-effect transistors: State-of-the-art. IEEE J. Electron Devices Soc. 2(4):44-49. https://doi.org/10.1109/JEDS.2014.2326622
- Choi W. Y., Park B. G., Lee J. D., Liu T. J. K., (2007), Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/Dec. IEEE Electron Device Lett. 28(8):743-745. https://doi.org/10.1109/LED.2007.901273
- Zhang, Q., Zhao W., Seabaugh A., (2006), Low-subthreshold-swing tunnel transistors. IEEE Electron Device Lett. 27(4):297-300.
- https://doi.org/10.1109/LED.2006.871855
- Sadeghi B., Ghammamy S., Gholipour Z., Ghorchibeigy M., Nia A. A., (2011), Gold/hydroxypropyl cellulose hybrid nanocomposite constructed with more complete coverage of gold nano-shell. Micro & Nano Letters. 6(4): 209-213. https://doi.org/10.1049/mnl.2011.0036
- Sadjadi M. S., Sadeghi B., Zare K., (2007), Natural bond orbital (NBO) population analysis of cyclic thionylphosphazenes, [NSOX (NPCl2) 2]; X= F (1), X= Cl (2). Journal of Molecular Structure: THEOCHEM. 817(1-3): 27-33. https://doi.org/10.1016/j.theochem.2007.04.015
- Seabaugh A. C., Zhang Q., (2010), Low-voltage tunnel transistors for beyond CMOS Logic. Proc IEEE. 98(12):2095–2110. https://doi.org/10.1109/JPROC.2010.2070470
- Ionescu A. M., Riel H., (2011), Tunnel field-effect transistors as energy efficient electronic switches. Nature. 479(7373):329-337. https://doi.org/10.1038/nature10679
- Bentrcia T., Djefal F., Ferhati H., Dibi Z., (2020), A comparative study on scaling capabilities of Si and SiGe nanoscale double gate tunneling FETs. Silicon. 12(4):945–953. https://doi.org/10.1007/s12633-019-00190-w
- Pandey C. K., Das D., Kadava R. K., Ashok T., AnilK. P., Siva R. G, (2023), A review on emerging tunnel FET structures for high-speed and low-power circuit applications. 2023 IEEE Devices for Integr.Circuit (DevIC). 163–167.
- https://doi.org/10.1109/DevIC57758.2023.10134784
- Agarwal S., Klimeck G., Luisier, M., (2010), Leakage-reduction design concepts for low-power vertical tunneling field-effect transistors. IEEE Electron Device Lett. 31(6): 621-623. https://doi.org/10.1109/LED.2010.2046011
- Avci U. E., Morris D. H., Young I. A., (2015), Tunnel field effect transistors: prospects and challenges. IEEE J. Elect. Dev. Soc. 3(3): 88–95.
- https://doi.org/10.1109/JEDS.2015.2390591
- Vladimirescu A., Amara A., Anghel C., (2012), An analysis on the ambipolar current in Si double-gate tunnel FETs. Solid-State Electron. 70: 67–72.
- https://doi.org/10.1016/j.sse.2011.11.009
- Kumar M.J., Janardhanan S., (2013), Doping-less tunnel field effect transistor: Design and investigation. IEEE Trans Electron Devices. 60(10):3285–3290.
- https://doi.org/10.1109/TED.2013.2276888
- Boucart K., Ionescu A.M., (2007), Double-gate tunnel FET with high-k gate dielectric. IEEE Trans Electron Devices. 54(7):1725–1733.
- https://doi.org/10.1109/TED.2007.899389
- Saurabh. S., Kumar. M. J., (2009), Impact of strain on drain current and threshold voltage of nanoscale double gate tunnel field effect transistor: Theoretical investigation and analysis. Jpn. J. Appl. Phys. 48(6R):064503. http://doi.org/10.1143/JJAP.48.064503
- Abdi D. B., Kumar. M. J., (2014), In-built N+ pocket p-n-p-n tunnel field-effect transistor. IEEE Electron Device Lett. 35(12): 1170–1172.
- https://doi.org/10.1109/LED.2014.2362926
- Cao W., Yao C. J., Jiao G. F., Huang D., Yu H. Y., Li M. F., (2011), Improvement in reliability of tunneling field-effect transistor with p-n-i-n structure. IEEE Trans Electron Devices. 58(7): 2122–2126. https://doi.org/10.1109/TED.2011.2144987
- Raad B. R., Nigam K., Sharma D., Kondekar P. N., (2016), Performance investigation of bandgap, gate material work function and gate dielectric engineered TFET with device reliability improvement. Superlattices Microstruct. 94: 138–146.
- https://doi.org/10.1016/j.spmi.2016.04.016
- Raad B. R., Sharma D., Nigam K., Kondekar P., (2016), Physics-based simulation study of high-performance gallium arsenide phosphide-indium gallium arsenide tunnel field-effect transistor. IET Micro. Nano Let. 11(7): 366-368.
- https://doi.org/10.1049/mnl.2016.0050
- Yang, Z., (2016). Tunnel field-effect transistor with an L-shaped gate. IEEE Electron Device Lett. 37(7):839-842. https://doi.org/10.1109/LED.2016.2574821
- Chen S., Wang S., Liu H., Li W., Wang Q., Wang X., (2017), Symmetric U-shaped gate tunnel field-effect transistor. IEEE Trans Electron Devices. 64(3): 1343-1349. https://doi.org/10.1109/TED.2017.2647809
- Choi W. Y., Lee. W., (2010), Hetero-gate-dielectric tunneling field effect transistors. IEEE Trans Electron Devices. 57(9): 2317–2319.
- https://doi.org/10.1109/TED.2010.2052167
- Lee M. J., Choi W. Y., (2012), Effects of device geometry on hetero-gate-dielectric tunneling field-effect transistors. IEEE Electron Device Lett. 33(10):1459–1461.
- https://doi.org/10.1109/LED.2012.2206790
- Madan. J., Chaujar R., (2017), Gate drain underlapped-PNIN-GAA-TFET for comprehensively upgraded analog/RF performance, Superlattices Microstruct., 102: 17–26. https://doi.org/10.1016/j.spmi.2016.12.034
- Ebrahimnia M., Ziabari, S. A. S., Kiani-Sarkaleh A., (2021), A design of improved nanoscale U-Shaped TFET by energy band modification for high performance digital and analog/RF applications. International Journal of Nano Dimension. 12(3): 279-292.
- https://doi.org/10.22034/IJND.2021.681127
- Shaker A., El Sabbagh M., El-Banna M. M., (2017), Influence of drain doping engineering on the ambipolar conduction and high-frequency performance of TFETs. IEEE Trans Elect. Dev. 64(9): 3541-3547. https://doi.org/10.1109/TED.2017.2724560
- Sahoo S., Dash S., Routray S. R., Mishra G. P., (2020), Impact of drain doping engineering on ambipolar and high-frequency performance of ZHP line-TFET, Semicond.Sci. Technol. 35(6): 065003. https://doi.org/10.1088/1361-6641/ab7ce7
- Garg S., Saurabh S., (2018), Suppression of ambipolar current in tunnel FETs using drain-pocket: Proposal and analysis. Superlattices Microstruct. 113: 261-270. https://doi.org/10.1016/j.spmi.2017.11.002
- Li C., Zhao X., Zhuang Y., Yan Z., Guo J., Han R., (2018), Optimization of L-shaped tunneling field-effect transistor for ambipolar current suppression and analog/RF performance enhancement. Superlattices Microstruct. 115: 154-167.
- https://doi.org/10.1016/j.spmi.2018.01.025
- Pandey C. K., Dash D., Chaudhury S., (2020), Improvement in analog/RF performances of SOI TFET using dielectric pocket. Int. J. Electron. 107(11): 1844-1860. https://doi.org/10.1080/00207217.2020.1756439
- Ebrahimnia M., Sedigh Ziabari S. A., Kiani-sarkaleh A, (2022), Influence analysis of dielectric pocket on ambipolar behavior and high-frequency performance of dual material gate oxide stack-double gate Nano-Scale TFET. J. Nanoanalysis.9(2): 90-98.
- https://doi.org/10.22034/jna.2022.1943631.1277
- Ebrahimnia M., Ziabari S. A. S., Kiani-sarkaleh A., (2023), Analytical modeling for a new structure of dielectric pocket-based dual material double gate TFET with gate oxide stack. Silicon. 15(7):3215-3224. https://doi.org/10.1007/s12633-022-02229-x
- Basak S., Asthana P. K., Goswami Y., Ghosh B., (2015), Leakage current reduction in junctionless tunnel FET using a lightly doped source. Applied Physics A. 118:1527-1533. https://doi.org/10.1007/s00339-014-8935-9
- Ghosh B., Akram M. W., (2013), Junctionless tunnel field effect transistor. IEEE Electron Device Lett. 34(5): 584-586. https://doi.org/10.1109/LED.2013.2253752
- Anand S., Amin S. I., Sarin, R. K., (2016), Performance analysis of charge plasma based dual electrode tunnel FET. Journal Semicond. 37(5): 054003.
- https://doi.org/10.1088/1674-4926/37/5/054003
- Hussain S., Mustakim N., Hasan M., Saha JK., (2021), Performance enhancement of charge plasma-based junctionless TFET (JL-TFET) using stimulated n-pocket and heterogeneous gate dielectric. Nanotechnology. 32(33):335206.
- https://doi.org/10.1088/1361-6528/abec07
- Bal P, Ghosh B, Mondal P., Akram, M. W., Tripathi, B. M. M., (2014), Dual material gate junctionless tunnel field effect transistor. J Comput Electron. 13:230–234.
- https://doi.org/10.1007/s10825-013-0505-4
- Xie H, Liu H, Wang S., Chen S., Han T., Li W., (2019), Improvement of electrical performance in heterostructure junctionless TFET based on dual material gate. Appl Sci. 10(1): 126. https://doi.org/10.3390/app10010126
- Sharma S., Chaujar R., (2022), Impact of tunnel gate process variations on analog/radio frequency (microwave) and small signal parameters of hetero‐material tunneling interfaced charge plasma junctionless tunnel field effect transistor. Int J Circuit Theory Appl. 50(10): 3626-3641. https://doi.org/10.1002/cta.3347
- Koppolu K., K C. R., (2024), The effect of a dual oxide-dual gate material and a sensitivity analysis on the performance of a junctionless tunnel FET. Silicon. 1-11.
- https://doi.org/10.1007/s12633-024-02964-3
- Sharma S., Chaujar R., (2022), RF, linearity and intermodulation distortion analysis with small-signal parameters extraction of tunable bandgap arsenide/antimonide tunneling interfaced JLTFET. Microsyst Technol. 28(12): 2659-2667.
- https://doi.org/10.1007/s00542-022-05273-0
- Vanak A., Amini A., Pishgar S. H., (2023), Improvements in reliability and RF performance of stacked gate JLTFET using p+ pocket and heterostructure material. Silicon. 15(9):4137-4147. https://doi.org/10.1007/s12633-023-02330-9
- Kumar K., Kumar A., Kumar V., Sharma, S. C., (2023), Comparative investigation of band gap and gate metal engineered novel Si0.2Ge0.8/GaAs charge plasma-based JLTFET for improved electrical performance. Silicon. 15(11):4689-4702. https://doi.org/10.1007/s12633-023-02387-6
- Kumar K., Kumar A., Sharma S. C., (2023), Electrical performance improvement of charge plasma-based junctionless TFET using novel coalescence of SiGe/GaAs and heterogeneous gate dielectric. Applied Physics A. 129(1): 23. https://doi.org/10.1007/s00339-022-06309-y
- Tirkey S., Sharma D., Yadav D. S., Yadav S., (2017), Analysis of a novel metal implant junctionless tunnel FET for better dc and analog/RF electrostatic parameters. IEEE Trans Electron Devices. 64(9):3943-3950.
- https://doi.org/10.1109/TED.2017.2730922
- Chandan B. V., Nigam K., Tirkey S., Sharma D., (2019), Metal-strip approach on junctionless TFET in the presence of positive charge. Appl Phys A. 125: 1–12.
- https://doi.org/10.1007/s00339-019-2966-1
- Vanak A., Amini A., (2024), Use of metal strip in stacked gate oxide JLTFET improves device quality and single-event-transient effect. Materials Science and Engineering: B. 307: 117526. https://doi.org/10.1016/j.mseb.2024.117526
- Kumar S., Goel E., Singh K., Singh B., Singh P. K., Baral K., Jit S., (2017), 2-D analytical modeling of the electrical characteristics of dual-material double-gate TFETs with a SiO2/HfO2 stacked gate-oxide structure. IEEE Trans Electron Devices. 64(3):960–968. https://doi.org/10.1109/TED.2017.2656630
- Eyvazi, K., Karami M. A., (2020), A new junction-less tunnel field-effect transistor with a SiO2/HfO2 stacked gate oxide for DC performance improvement. 2020 28th Iran. Conf. Electr. Eng. (ICEE). pp. 1–4. https://doi.org/10.1109/ICEE50131.2020.9260621
- Tripathi SL., Patel R., Agrawal V. K., (2019), Low leakage pocket junction-less DGTFET with biosensing cavity region. Turkish J Electr Eng Comput Sci. 27(4): 2466–2474. https://doi.org/10.3906/elk-1807-186
- Tirkey S., Nigam K., Pandey S., Sharma D., Kondekar P., (2017), Investigation of gate material engineering in junctionless TFET to overcome the trade-off between ambipolarity and RF/linearity metrics. Superlattices Microstruct. 109: 307-315.
- https://doi.org/10.1016/j.spmi.2017.03.059
- Aghandeh H, Ziabari S. A. S., (2017), Gate engineered heterostructure junctionless TFET with Gaussian doping pro le for ambipolar suppression and electrical performance improvement. Superlattices Microstruct. 111: 103–114.
- https://doi.org/10.1016/j.spmi.2017.06.018
- Kumar K., Kumar A., Kumar V., Jain A., Sharma S. C., (2023). Ambipolarity suppression of band gap and gate dielectric engineered novel Si0. 2Ge0. 8/GaAs JLTFET using gate overlap technique. Silicon. 15(18): 7837-7854.
- https://doi.org/10.1007/s12633-023-02624-y
- ATLAS device simulator, Silvaco Inc. Santa Clara (2018).
- Zhao Y., Wu C., Huang Q., (2017), A novel tunnel FET design through adaptive bandgap engineering with constant sub-threshold slope over 5 decades of current and high ION/IOFF ratio. IEEE Electron Device Lett. 38: 540–543.
- https://doi.org/10.1109/LED.2017.2679031
- Bagga N., Chauhan N., Banchhor S., Gupta D., Dasgupta S., 2019, Demonstraion of a novel tunnel FET with channel sandwiched by drain. Semicond. Sci. Technol. 35(1): 015008. https://doi.org/10.1088/1361-6641/ab5434
- Johnson R.W., Hultqvist A., Bent S. F., (2014), A brief review of atomic layer deposition: from fundamentals to applications. Mater. Today. 17(5): 236-246.
- https://doi.org/10.1016/j.mattod.2014.04.026
- Na KY., Kim YS., (2006), Silicon complementary metal-oxide-semiconductor field-effect transistors with dual work function gate. Japanese J Appl Physics. 45(12R):9033.
- https://doi.org/10.1143/JJAP.45.9033
- Verma P. K., Gupta S. K., (2021), An improved analog/RF and linearity performances with small-signal parameter extraction of virtually doped recessed source/drain dopingless junctionless transistor for radio-frequency applications. Silicon. 13(5):1519–1539. https://doi.org/10.1007/s12633-020-00518-x
- Nigam K., Singh S. V., Kwatra, P., (2021), Investigation and design of stacked oxide polarity gate JLTFET in the presence of interface trap charges for analog/RF applications. Silicon. 14:1-18. https://doi.org/10.1007/s12633-021-01162-9
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