Simulation for a low-energy ternary multiplier cell based on Graphene nanoribbon field-effect transistor

Abstract

The multiplier circuit is considered to be a significant component of larger circuits, such as the arithmetic and logic unit (ALU), and it is crucial to enhance its energy efficiency. This objective can be easily achieved by utilizing graphene nanoribbon field-effect transistor (GNRFET) devices and adopting ternary logic. Ternary circuit designs demonstrate superior energy efficiency and occupy less space compared to binary ones. The adjustability of the threshold voltage (V_th) in GNRFET devices is directly influenced by the width of the graphene nanoribbon (GNR). This offers significant advantages for ternary circuit designs. This paper presents a 24-transistor low-energy GNRFET-based single-trit ternary multiplier. Our proposed design incorporates an enhanced voltage division technique to achieve logic â1â while minimizing power consumption. The primary design approach employed in our design involves the utilization of unary operators and specialized transistor configurations to reduce the number of transistors and shorten the critical path. We used the Hewlett simulation program with integrated circuit emphasis (HSPICE) and GNRFET technology with a 32-nm channel length operating at 0.9 V and 300Ë K to evaluate the efficiency of our circuit. We then compared it with similar existing ternary multiplier circuits. The suggested circuit displays favorable delay and power consumption characteristics and ranks as the second most optimal design in terms of energy efficiency. Furthermore, it improves the energy-delay-product by at least 2.80%.