10.30495/ijsee.2022.1935935.1126

Design of Fault-Tolerant XOR/XNOR Gate Using Fault-Tolerant NNI Gate

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  • Fatemeh Kiayi1,
  • Behnaz Gharekhanlou*2,
  • Alireza Kashaninya3,
  1. Department of Electrical Engineering, Central Tehran Branch, Islamic Azad University, Tehran, Iran
  2. Department of Electrical Engineering, Central Tehran Branch, Islamic Azad University, Tehran, Iran.
  3. Electrical Engineering Department, Central Tehran Branch, Islamic Azad University, Tehran, Iran

Revised: 2021-07-20

Accepted: 2021-08-18

Published in Issue 2023-09-01

How to Cite

Kiayi, F., Gharekhanlou, B., & Kashaninya, A. (2023). Design of Fault-Tolerant XOR/XNOR Gate Using Fault-Tolerant NNI Gate. International Journal of Smart Electrical Engineering, 12(3), 229-235. https://doi.org/10.30495/ijsee.2022.1935935.1126
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Abstract

Today more than ever, we need high-speed circuits with low occupancy and low power as an alternative to CMOS circuits. Therefore, we proposed a new path to build nanoscale circuits such as Quantum-dot Cellular Automata (QCA). This technology is always prone to failure due to its very small size. Therefore, designers always try to design fault-tolerant gates and provide methods to increase the reliability of QCA. By adding redundant cells, the possibility of some defects such as cell omission and cell addition is somewhat reduced. However, in the face of defects such as stuck-at 0/1 faults, Clock fault and bridging fault. We can greatly increase the fault tolerance by appropriate placement and using fault tolerant gates with a suitable structure. In this paper, we design the XOR/XNOR gate with the approach of preventing stuck-at 0/1 fault, clock fault, and bridging fault using the first NNI gate tolerating cell addition fault.
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