OICC Press Signal Processing and Renewable Energy (SPRE) 2588-7335 10 1 2026 03 31 Improved PDP of the Open-Loop Phase-FrequencyDetector to Reduce the Output Jitter of Phase-Locked Loop Circuits in CMOS Technology 10.57647/spre.2026.1001.03 EN MohammadSadegh Zarbakhsh Department of Electrical Engineering, Mahs.C., Islamic Azad University, Mahshahr, Iran Behzad Ghanavati Department of Electrical Engineering, Mahs.C., Islamic Azad University, Mahshahr, Iran Pejman Shaabani Department of Electrical Engineering, Mahs.C., Islamic Azad University, Mahshahr, Iran Sajad Tabatabaee Tabatabaee Department of Electrical Engineering, Mahs.C., Islamic Azad University, Mahshahr, Iran Journal Article 2026 03 31 A new phase-locked loop (PLL) with an improved open-loop phase-frequency detector block (PFD) with a dead zone close to zero and a compatible charge pump (CP) to reduce the power consumption and the dead zone and output jitter is proposed. Since in all phase-locked loop systems, phase-frequency detector and charge pump elements are designed and used separately, inherently, detecting the phase difference by the phase-frequency detector and applying it to the charge pump circuit requires time. This time creates a dead zone in the entire phase-locked loop system and causes a jitter in the phase-locked loop. This paper solves this challenge by combining PFD and CP blocks. This structure's proposed design and simulation results show that the overall phase-locked loop system has a very low output jitter due to the significant reduction of the dead zone and the integration of the phase-frequency detector blocks and the charge pump. The simulations carried out in 90 nm CMOS technology indicate also a reduction in power consumption to 85 microwatts, a dead zone close to zero, and an operating frequency of 4.2 GHz, phase noise is -123dBc/Dec and the results of which have been compared with previous works. Monte-Carlo simulation from post-layout simulation is carried out and the result is that the average power consumption ranged from a minimum of 61.4 microwatts to a maximum of 101.6 microwatts, and the delay and PDP also changed from 36.6ps to 59.1ps and 3.22 to 4.23, respectively.