OICC Press Majlesi Journal of Electrical Engineering 2345-3796 9 1 2024 02 20 A Digital Ground Distance Relaying Algorithm to Reduce the Effect of Fault Resistance during Single Phase to Ground and Simultaneous Faults EN Mohammad Razaz Department of Electrical Engineering, Shahid Chamran University of Ahvaz, Iran Seyyed Ghodratollah Seifossadat Department of Electrical Engineering, Shahid Chamran University of Ahvaz, Iran Morteza Razaz Department of Electrical Engineering, Shahid Chamran University of Ahvaz, Iran Mahmood Joorabian Department of Electrical Engineering, Shahid Chamran University, Ahvaz, Iran Journal Article 2024 02 20 This paper intends to provide an algorithm of fault resistance compensation for digital ground distance relay considering the voltage and current transformer effects. Performance of the conventional ground distance relaying manner is adversely affected by different ground faults and also typical type, called a simultaneous open conductor and ground fault. The proposed scheme by using local-end data only, has shown satisfactory performances under wide variations in fault location, with different values of fault resistance and having positive and negative of power transfer angle. The presented method which has been carried out on the IEEE 14 bus benchmark is executed in PSCAD/EMTDC and MATLAB software and the results show the accurate performance of mention configuration.