OICC Press Majlesi Journal of Electrical Engineering 2345-3796 6 3 2024 02 25 Design Issues for Low Voltage Low Power CMOS Folded Cascode LNAs EN Ehsan Kargaran sadjad institue of higher education, mashhad Mohammad Javad Zavarei Microelectronic Laboratory, Sadjad Institute of Higher Education, Mashhad, Iran Nahid Fatahi Microelectronic Laboratory, Sadjad Institute of Higher Education, Mashhad, Iran Seyedeh Sara Hassani Microelectronic Laboratory, Sadjad Institute of Higher Education, Mashhad, Iran Khalil Mafinezhad Sadjad Institute of Higher Education, Mashhad, Iran Hooman Nabovati Department of Electrical Engineering, Sadjad Institute of Higher Education, Mashhad Journal Article 2024 02 25 Design and simulation results of fully integrated 5-GHz CMOS LNAs are presented in this paper. Three different input impedance matching techniques are considered. Using a simple L-C network, the parasitic input resistance of a MOSFET is converted to a 50 Ω resistance. As it is analytically proven, that is because the former methods enhance the gain of the LNA by a factor that is inversely proportional to MOSFET’s input resistance. The effect of each input impedance matching on the amplifier’s noise figure and gain is discussed. By employing the folded cascode configuration, these LNAs can operate at a reduced supply voltage and thus lower power consumption. To address the issue of nonlinearity in design of low voltage LNAs, a new linearization technique is employed. As a result, the IIP3 is improved extensively without sacrificing other parameters. These LNAs consume 1.3 mW power under a 0.6 V supply voltage.