<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE ArticleSet PUBLIC "-//NLM//DTD PubMed 2.7//EN" "https://dtd.nlm.nih.gov/ncbi/pubmed/in/PubMed.dtd">
<ArticleSet>
<Article>
<Journal>
<PublisherName>OICC Press</PublisherName>
<JournalTitle>Majlesi Journal of Electrical Engineering</JournalTitle>
<Issn>2345-3796</Issn>
<Volume>18</Volume>
<Issue>1</Issue>
<PubDate PubStatus="epublish">
<Year>2024</Year>
<Month>04</Month>
<Day>21</Day>
</PubDate>
</Journal>
<ArticleTitle>High-Speed Current-Mode Full-Adder with Carbon Nanotube Technology</ArticleTitle>
<VernacularTitle></VernacularTitle>
<FirstPage></FirstPage>
<LastPage></LastPage>
<ELocationID EIdType="doi">10.30486/mjee.2023.1993248.1203</ELocationID>
<Language>EN</Language>
<AuthorList>
<Author>
<FirstName>Mehdi</FirstName>
<LastName>Habibollahi</LastName>
<Affiliation>Department of Computer Engineering, Najafabad Branch, Islamic Azad University, Najafabad, Iran</Affiliation>
<Identifier Source="ORCID"></Identifier>
</Author>
<Author>
<FirstName>Ali</FirstName>
<LastName>Saghafinia</LastName>
<Affiliation>Department of Mechanical Engineering, Isfahan (Khorasgan) Branch, Islamic Azad University, Isfahan, Iran</Affiliation>
<Identifier Source="ORCID">0000-0002-5056-2672</Identifier>
</Author>
</AuthorList>
<PublicationType>Journal Article</PublicationType>
<History>
<PubDate PubStatus="received">
<Year>2024</Year>
<Month>04</Month>
<Day>21</Day>
</PubDate>
</History>
<Abstract>The relationship between the amount of energy consumption and the circuit speed to change the design efficiency is an important challenge in designing digital circuits. Adders are essential components of computing circuits that play an important role in computing speed. This article proposed a new design for a single-bit current mode full adder using the field effect transistors based on carbon nanotubes to enhance the speed and reduce the occupied space on the chip. The correct combination of the majority function, the current mirror technique, and the sum value on carry reduced the delay of all adder circuits. The simulations have been done by HSPICE software and based on the provided standard model of 32 nm with CNTFET technology. The proposed design has improved by 55% in terms of delay. The PDP level in the proposed design has decreased by 63% compared to the previous designs.</Abstract>
<ObjectList>
<Object Type="keyword">
<Param Name="value">Carbon Nanotubes</Param>
</Object>
<Object Type="keyword">
<Param Name="value">current mode</Param>
</Object>
<Object Type="keyword">
<Param Name="value">Field Effect Transistors</Param>
</Object>
<Object Type="keyword">
<Param Name="value">Full adder</Param>
</Object>
<Object Type="keyword">
<Param Name="value">Majority Function</Param>
</Object>
</ObjectList>
</Article>
</ArticleSet>