OICC Press Majlesi Journal of Electrical Engineering 2345-3796 19 3 2025 09 25 Design of 65nm 6T SRAM Using Improved Sense Amplifiers and Write Driver Circuits 10.57647/j.mjee.2025.17413 EN Quang Vinh Truong Faculty of Electrical and Electronics Engineering, Ho Chi Minh City University of Technology, Vietnam National University – Ho Chi Minh, Ho Chi Minh City, Vietnam https://orcid.org/0000-0002-9085-3247 Tuan Dat Tieu Faculty of Electrical and Electronics Engineering, Ho Chi Minh City University of Technology, Vietnam National University – Ho Chi Minh, Ho Chi Minh City, Vietnam Journal Article 2025 09 25 Designing high-speed 6T SRAM for efficient read and write operations poses a significant challenge for circuit designers. In this paper, we propose a 65nm 6T SRAM architecture using sense amplifiers and write driver circuits to enhance the read and write performance. The sense amplifier helps the reading process go faster and the reading data be more stable. The write driver is designed with a symmetrical structure to reduce the write delay. In addition, the control circuit performs the checking process to synchronize read operations, optimize latency without interruption. The simulation result shows that the read delay and write delay are 58.66ps and 79.67ps, respectively. These delays outperform most of the other study.