TY - EJOUR
AU - Tayal, Shubham
AU - Samrat, Pachimatla
AU - Keerthi, Vadula
AU - Jena, Biswajit
AU - Rajendra, Karthik
PY - 2024
DA - February
TI - Conventional vs. junctionless gate-stack DG-MOSFET based CMOS inverter
T2 - International Journal of Nano Dimension (Int. J. Nano Dimens.)
VL - 12
L1 - https://oiccpress.com/international-journal-of-nano-dimension/article/conventional-vs-junctionless-gate-stack-dg-mosfet-based-cmos-inverter/
DO - 10.22034/ijnd.2021.677807
N2 - In this article, the high-k gate dielectric effect on the operation of complementary metal oxide semiconductor (CMOS) inverter build using conventional (CL) double-gate (DG) metal oxide semiconductor field effect transistor (MOSFET) and junctionless (JL) double-gate (DG) MOSFET has been explored. It is found that the improvement in inverter performance is more pronounced in CL-DG-MOSFET based CMOS inverter in comparison to JL-DG-MOSFET based CMOS inverter when SiO2 is replaced by the high-k dielectric at gate oxide. The improvement in low noise margin (ΔNML), high noise margin (ΔNMH), gain (ΔA) & propagation delay (Δp < sub>d) is 3.19%, 1.64%, 5.2% & 0.9% respectively when SiO2 is replaced by TiO2 at gate oxide in case of CL-DG-MOSFET based CMOS inverter whereas it is 1.96%, 1.24%, 3.4% & 1.71% respectively in case of JL-DG-MOSFET based CMOS inverter. Consequently, the utilization of high-k dielectric as gate oxide is more advantageous in CL-DG-MOSFET devices for improved stability and gain of CMOS inverter.
IS - 2
PB - OICC Press
KW - Gate-Stack, High-k, Junctionless, CMOS Inverter, DG-MOSFET 
EN -