TY - EJOUR
AU - Atmakuri, Murali Krishna
AU - Kumar, Chunduri Kiran
AU - Nagalakshmi, Kanneganti
AU - Chaitanya, Morsa
PY - 2024
DA - March
TI - Performance enhancement of flipped voltage follower current mirror in nanoscale technology
T2 - International Journal of Nano Dimension (Int. J. Nano Dimens.)
VL - 15
L1 - https://oiccpress.com/international-journal-of-nano-dimension/article/performance-enhancement-of-flipped-voltage-follower-current-mirror-in-nanoscale-technology/
DO - 10.57647/j.ijnd.2024.1502.14
N2 - The trend of technology downscaling to accommodate low supply requirement has been a continuous motivation for the IC industry. The nanoscale dimension MOSFET demands low supply but at the same time results in poor performance of analog circuits due to MOSFET secondary effects. In this paper, a fundamental block of current mode circuit, current mirror is proposed designed using MOSFET in nanoscale technology. The performance enhancement is done using modified structure of recently reported low voltage cell, flipped voltage follower. The modification incorporates cascoding of self cascode stage in flipped voltage follower. Further enhancement of this configuration is done in terms of MOSFET operating region for which quasi-floating gate technique is adopted. As a result, the final proposed quasi-floating gate based flipped voltage follower structure results is extremely low impedance at its output node compared to conventional flipped voltage follower. This property helps to achieve the ideal requirement of current mirror’s input resistance. For output resistance the regulated cascode super cascode modified again with quasi-floating gate technique is used. The proposed current mirror results in input resistance of 81 ohms have been showed output resistance of 112 giga ohms & bandwidth of 2.8 giga hertz. The proposed circuit is designed using MOS technology of 180 nanometer & analyzed using Spice simulator at a dual polarity supply of 0.5 volt.
IS - 2
PB - OICC Press
KW - Current Mirror, FVF, Quasi Floating Gate, Input Resistance, Output Resistance, Self-Cascode 
EN -