Representation of heterostructure electrically doped nanoscale tunnel FET with Gaussian-doping profile for high-performance low-power applications

Introduction

In recent years, the scaling of conventional CMOS transistors and supply voltage have been faced with problems such as high off-state current, SCEs, DIBL, and subthreshold swing limits of 60 mV/dec at room temperature [ ¹ , ² – ³ ]. Therefore, some various device structures such as double gate [ ⁴ ], tri-gate [ ⁵ ], gate-all-around (GAA) MOSFET [ ⁶ ], and junctionless field-effect transistor JLFET [ ⁷ ] have been reported. JLFET has been fabricated without using PN junctions at the lateral junctions. Although it simplifies the fabrication process, it also suffers from the high off-state current. Tunneling field-effect transistors (TFETs) recently replaced the conventional MOSFET due to its steeper subthreshold swing (SS) (< 60 mV/dec) and low off-state current ( I _off ) which leads to the low values of power consumption [ ⁸ , ⁹ , ¹⁰ , ¹¹ – ¹² ]. The achievement was obtained due to the band-to-band tunneling (BTBT) carriers rather than drift–diffusion over the barrier. One of the drawbacks of the performance of TFETs is the inferior on-state current ( I _on ) because of the insufficient quantum BTBT limited by the large bandgap of silicon. Hence, it can be solved using low bandgap semiconductors [ ¹³ ]. Lately, different methods of improving the performance of TFETs have been presented such as gate engineering [ ¹⁴ ], using heterostructures and high- k dielectric [ ¹⁵ ]. TFETs also suffer from ambipolar behavior [ ¹⁶ , ¹⁷ ], which is concluded from the presence of symmetric areas of P ⁺ and N ⁺ in the source and the drain, the overlapping between the valence band of the channel, and the conduction band of the drain under negative gate bias. In this condition, the channel is accumulated by holes due to BTBT at drain/channel interface. Therefore, it has created a high current drive at the negative voltage similar to the positive voltage. To overcome the ambipolar behavior, researchers have used hetero-gate dielectrics, gate workfunction engineering, asymmetric doping for source and drain [ ¹⁸ ], Gaussian-doping profiles, and gate–drain overlapping [ ¹⁴ , ¹⁶ , ¹⁷ , ¹⁹ – ²² ].

Another drawback in the down-scaling process of TFETs is to fabricate metallurgical junctions due to the need for the creation of abrupt junctions at high temperatures which is difficult and expensive [ ⁷ ]. This problem can be solved using junctionless TFETs (JLTFETs) [ ²² , ²³ ]. JLTFET uses high-doping concentrations in the drain, channel, and source. It has provided N ⁺ –I–P ⁺ for N-JLTFETs similar to doping profile of an N-TFET using two methods. One method is the use of the charge plasma concept, wherein the desired doping profile is created by choosing appropriate workfunctions for the gates called the polarity gate (PG) located at the source region and the control gate (CG) located at the middle with a lower workfunction than PG for being a nearly intrinsic channel [ ²⁴ , ²⁵ , ²⁶ – ²⁷ ]. As the same way, p-channel JLTFET has the similar structure [ ²⁸ ]. Another method to create N ⁺ –I–P ⁺ in JLTFET is using the electrically doped concept, in which P ⁺ region underneath PG is created by applying an appropriate external bias voltage. These devices are known as EDTFET [ ²⁹ , ³⁰ – ³¹ ]. The other type of JLTFETs known as dopingless TFETs suppresses the need of a higher thermal budget and expensive thermal annealing technique due to refusing the physical doping [ ³² , ³³ , ³⁴ , ³⁵ – ³⁶ ]. In this structure, the drain region is also gated for creating N ⁺ using charge plasma or electrically doped concepts. JLTFETs also include inferior I _on and ambipolar behavior. To overcome these problems, different methods have been investigated, such as: using heterostructures at source/channel interfaces [ ³⁷ , ³⁸ , ³⁹ , ⁴⁰ – ⁴¹ ], the assumption of gate workfunction engineering [ ⁴² , ⁴³ , ⁴⁴ – ⁴⁵ ], the adoption of hetero-gate dielectrics [ ⁴⁶ , ⁴⁷ , ⁴⁸ – ⁴⁹ ], using Gaussian-doping profiles [ ²² , ⁵⁰ , ⁵¹ ], applying source pockets [ ⁵² ], the consideration of strain engineering [ ⁵³ , ⁵⁴ ], using ferroelectric insulators [ ⁴⁰ ], and drain workfunction engineering for DLTFET [ ⁵⁵ , ⁵⁶ ].

The rest of this paper is structured as follows. In Sect.  ² , device simulations and structures are discussed. In Sect.  ³ , the DC characteristics for the GaSb–EDTFET are presented which clarify its improvements in analog applications over a basic Si-EDTFET. In Sect.  ⁴ , Gaussian-doping distribution is proposed to decrease the ambipolar current. Section  ⁵ is dedicated to the analysis and calculation of analog parameters, cut-off frequency, and transconductance for the GD–GaSb–EDTFET. In Sect.  ⁶ , heterostructure channel/source interface EDTFET is studied which applies Al _x Ga _{1− x} Sb for the channel and drain regions and GaSb for the source region (AlGaSb–GaSb–EDTFET). With respect to the Al fraction ( x ), the bandgap energy of Al _x Ga _1-x Sb and, consequently, the tunneling probability and the device current vary. Thus, the optimal Al composition is extracted in AlGaSb based on the improving ambipolar current, off-current, on-current, on-to-off current ratio, threshold voltage, and subthreshold swing. Then, it is presented a performance comparison between the structures in DC parameters is presented. Section  ⁷ concludes this paper.

Device structure and simulation

A cross-sectional view of conventional Si-EDTFET is shown in Fig.  ¹ a, GD–GaSb–EDTFET in Fig.  ¹ b and GD–AlGaSb–GaSb−EDTFET in Fig.  ¹ c. A III–V semiconductor has been used in the GD–GaSb–EDTFET, which has a narrow bandgap (0.72 eV) and high carrier mobility [ ⁵⁷ , ⁵⁸ ]. In the GD–AlGaSb–GaSb–EDTFET device, GaSb is used at the source side and AlGaSb at the drain and the channel sides to improve the device performance. It is considered that the channel, source, and drain are heavily n-type doped (1 × 10 ¹⁹  cm ⁻³ ) in the case of the conventional EDTFET. For the proposed devices (GD–GaSb–EDTFET and GD–AlGaSb–GaSb–EDTFET), Gaussian-doping profile is allocated to channel and drain, although source is kept the uniform doping. All devices consist of two isolated gates (CG and PG) with the same workfunction equal to 4.7 eV. The polarity gate bias voltage VPG = − 1.2 V has been considered for obtaining the desired carriers concentration in the source region. It also provides a concentration gradient at the source/channel interface [ ³⁰ , ³¹ ]. In addition, the spacer length (Lgap) is kept 5 nm for creating N ⁺ -doped pocket layer near to the source. The doping profile of N ⁺ –I–N ⁺ –P ⁺ TFET is formed by electrical doped concept rather than physical doping. High- k dielectric was also used to improve the subthreshold swing and on-state current [ ¹⁵ ]. The rest of the device design parameters used in the simulations are listed in Table  ¹ .

Fig. 1

All the electrical characteristics were obtained from 2D ATLAS device simulator [ ⁵⁹ ]. A nonlocal BTBT model to calculate band-to-band tunneling of charge carriers between source and channel was included. In this model, the spatial variation of energy bands is taken into account and also the recombination–generation rate at each location is considered based on the electric field to model the tunneling process. The Shockley–Read–Hall model was also used to incorporate the minority recombination due to the presence of high-impurity concentration in the channel and the interface trap effect. It takes into consideration the phonon transitions that occur in the presence of defects or traps within the forbidden gap of the semiconductor. Fermi–Dirac statistics was invoked to calculate the intrinsic carrier concentration required in the expressions for SRH recombination. Auger recombination is a non-radiative process involving three carriers. It occurs when an electron and hole recombine, but instead of producing light, either an electron is raised higher into the conduction band or a hole is pushed deeper into the valence band. Auger recombination is significant in non-equilibrium conditions when the carrier density is very high. To consider this effect, auger recombination model was included. High doping often leads to narrowing of bandgap and is essential to consider especially within the devices which are based on tunneling mechanism. Therefore, bandgap narrowing model is also incorporated. The quantum confinement model was activated to consider quantum confinement effects on BTBT.

DC-performance analysis

In this section, The DC performance and the comparison of Si and GaSb based on electrically doped concept have been analyzed. Tunneling devices have transported the phenomena entirely different from bulk MOSFET devices. Drive current in TFETs is computed based on band-to-band tunneling from the valence band of source to the conduction band of channel. Electron/hole tunneling probability in this research is calculated using the nonlocal BTBT model on the basis of the Wentzele–Kramere–Brillouin method. Band-to-band tunneling probability strongly depends on material/device parameters such as the screening tunneling barrier length (Λ), energy bandgap (Eg), band energy difference between the valence and conduction bands of tunneling regions (ΔΦ), and effective mass of charge carriers ( m ^∗ ), according to Eq. ( ¹ ) [ ³ , ⁶⁰ – ⁶² ], wherein h and q are the Planck constant and electron charge, respectively:

Tunneling barrier length (Λ) given by Eq. ( ² ) is sensitive to the dielectric thickness ( t _ox ), semiconductor channel thickness ( t _Si ), dielectric constant of the gate material, and semiconductor ( ε _Si , ε _ox ):

In the N-TFET device, drain is always biased with positive voltage to allow the connections between source–channel and the drain–channel will be in reverse bias. Device current is proportional to tunneling probability, which itself depends on the variation of band structure at the source/channel and drain/channel interfaces. The band structure is changed by varying gate and drain voltages. By overlapping the conduction band with the valence band, tunneling probability is increased at regions. At on state, under the positive gate voltage, an overlap occurs between the conduction band of the channel and the valence band of the source. According to Eq. ( ¹ ), to increase on-state current of EDTFETs, lower bandgap material can be used. In Fig.  ² , it is observed that the on-state current in case of GaSb–EDTFET is higher due to the presence of lower bandgap (0.72 V) of gallium antimonide. At the ambipolar state, in which negative gate voltage is applied, an overlap is created between the conduction band of the drain and the valence band of the channel. Therefore, the ambipolar current is also increased in case of GaSb–EDTFET by applying lower bandgap material. Increasing current is explainable based on the energy band diagram. In Fig.  ³ a, b, it can be observed that the tunneling barrier length is narrow at the drain/channel interface (at off state) and is also thin at the source/channel interface (at on state) in case of GaSb–EDTFET. The electron-tunneling rate can also represent the increasing current. Figure  ³ c shows the higher electron-tunneling rate for GaSb–EDTFET at on state. The current is also proportional to the electron-tunneling rate, which depends on the transmission probability, according to Eq. ( ¹ ). Therefore, the on-state current significantly increases due to the improving tunneling rate.

Fig. 2

Fig. 3

Gaussian-doping profile

To reduce off and ambipolar current, the tunneling barrier length at the drain/channel interface must be increased at off and ambipolar states, which can be achieved by applying the Gaussian-doping profile [ ⁵¹ ]. Based on the results obtained from Sect.  ³ , the GaSb–EDTFET has higher on-current than the Si-EDTFET. To improve the performance of the GaSb–EDTFET in digital applications, in addition to analog applications, along with increasing the on-current, reducing the off and ambipolar current is considered. Therefore, in this section, the impact of the Gaussian-doping profile on the performance of the GaSb–EDTFET is studied by applying it in the drain and channel. Figure  ⁴ illustrates the contour plot of the Gaussian net doping of the device. Accordingly, source is n-type-doped uniformly with a concentration of 1 × 10 ¹⁹  cm ⁻³ . The peak of Gaussian doping is at the source/channel interface and diminishes exponentially along the channel to drain. Thus, a lower concentration is observed at the channel and drain regions. The lower number of electrons tunneling at the drain/channel interface using Gaussian doping supports the reduction of the off and ambipolar current.

Fig. 4

In Atlas, Gaussian doping is defined, according to the following equation:

The decrease of the off and ambipolar current by applying Gaussian doping to GaSb–EDTFET device (GD–GaSb–EDTFET) is shown in Fig.  ⁵ . Energy band diagram of the structures at off state, wherein gate voltage is zero, is represented in Fig.  ⁶ a. It illustrates that no overlap happens between the conduction band of the channel and the valence band of the source. It is also observed that the tunneling barrier length is higher by applying Gaussian doping. Therefore, at off state, according to Eq. ( ¹ ), the probability of the tunneling is diminished, and consequently, the current is reduced. Similarly, it accrues at ambipolar state. The electric field is obtained from the gradient of the energy band diagram. As can be seen in Fig.  ⁶ b, there are two peaks at source/channel and drain/channel interfaces in the electric field profile of GaSb–EDTFET, because the doping profile is N ⁺ –I–P ⁺ . In the GD–GaSb–EDTFET, the gradient of the energy band diagram at drain/channel interface is neglected due to Gaussian-doping profile; consequently, the electric field profile at this interface is negligible; therefore, the off current is reduced. The ambipolar performance is also similar to off state.

Fig. 5

Fig. 6

The performance of the device in the subthreshold region is often based on the subthreshold swing. Point subthreshold swing (SS _p ) represents the reverse of the slope of the transfer characteristic under log scale for Ids. Since the average subthreshold swing (SS _ave ) is independent of the step size of gate voltage, it is more common to use. The entire range of gate voltage up to threshold voltage ( V _th ) is used to calculate SS _ave , according to Eq. ( ⁴ ) [ ¹³ , ¹⁹ ]:

Analog performance

In this section, the analog performance of the GD–GaSb–EDTFET compared to the conventional EDTFET is analyzed. Cut-off frequency ( f _T ) and transconductance (gm) of the structures are obtained and compared. The parameter gm is the ratio of the variation in the drain current to the variation in the gate voltage of the device. By increasing the gate–source voltage, the number of electrons injected from the source\channel interface is incremented due to the quantum-tunneling phenomenon; therefore, the gm parameter is increased which has the significant role to determine cut-off frequency.

The parameter f _T , determined by f _T  = gm/2 π Cgg, is evoked from a small-signal ac solution at a frequency of 1 MHz, wherein Cgg represents the total gate capacitance and is defined by CG = ∂Qch/∂Vgs. Qch is the total charge in the channel. By assuming a good gate electrostatic control, the parasitic capacitance can be negligible [ ⁶¹ ]. Therefore, it is considered that the charge in the channel and gate is the same. Significantly enhancement analog performance of GD–GaSb–EDTFET is observed in terms of gm and f _T compared to the conventional EDTFET in Fig.  ⁷ a, b.

Fig. 7

Heterostructure EDTFET

In the previous section, the ambipolar and off current were decreased using the Gaussian-doping profile. In the rest of this research, heterostructure channel/source interface EDTFET is investigated. Heterostructure TFETs employ a low bandgap material at the source region resulting in the improved on-current. However, the ambipolar behavior can be suppressed using a wide bandgap material at the source and drain side. Therefore, the AlGaSb at the channel and drain side and the GaSb at source side are chosen with the uniformly doping profile. To optimize the performance of the heterostructure device, more mole fraction x of aluminum is investigated in the drain and channel side as Al _x Ga _{1- x} Sb. By increasing the Al fraction, the bandgap energy of Al _x Ga _{1- x} Sb becomes larger, and as a result, the tunneling probability at the channel/drain interface decreases according to Eq. ( ¹ ). The transfer characteristic of the heterostructure EDTFET with different Al composition (x) values is presented in Fig.  ⁸ . It is observed that, by the increment of the value of x , off current is effectively reduced and consequently suppressed the ambipolar behavior because of gate-induced drain leakage (GIDL) at the drain and channel junction. The extracted I _on , I _off , I _on / I _off ratio, I _amb , SS _ave, and V _th as a function of Al composition are illustrated in Fig.  ⁹ . It is explicit that I _on , I _off, and I _amb reduce by increasing of mole fraction x . Therefore, higher I _on , lower I _amb, and I _off cannot occur at the same time. Hence, by trading-off between the above parameters, Al mole fraction is chosen 10% ( x  = 0.1). In spite of reducing on-current by increasing Al mole fraction, as shown in Fig.  ⁸ , I _on is still improved compared to the conventional Si-EDTFET, in addition to reduce I _off , I _amb by selecting 0.1 for Al mole fraction. By extracting from the transfer characteristic (Id–Vgs) of Al _0.1 GaSb–GaSb–EDTFET device, I _on is 0.25 mA/μm, I _off is 2.2 × 10 ⁻¹⁸  A/μm, I _amb is 3 × 10 ⁻¹⁸  A/μm, V _th is 0.63 V, and SS _ave is 59 mV/dec.

Fig. 8

Fig. 9

In the following, the combination of the two above methods, heterostructure and Gaussian-doping profile, on EDTFET (GD–Al _0.1 GaSb–GaSb–EDTFET) is investigated and DC parameters’ device is obtained using the extract of transfer characteristic (Id-Vgs). SS _p is 37 mV/dec, I _on is 6.2 × 10 ⁻⁵  A/μm, I _off is 1.7 × 10 ⁻¹⁹  A/μm, I _on / I _off ratio is 3.6 × 10 ¹⁴ , and I _amb is 1.3 × 10 ⁻²³  A/μm. Therefore, it is clear that I _amb has declined sharply.

Figure  ¹⁰ shows a comparison between the two methods and the blend of them based on Id–Vgs curve. As it is explicit from the figure, the method of the applying Gaussian-doping profile, GD–GaSb–EDTFET, and the use of the heterostructure (Al _0.1 GaSb–GaSb–EDTFET) results in almost the same decrease in I _amb . However, by combining these two methods, GD–Al _0.1 GaSb–GaSb–EDTFET, I _off is decreased and I _amb is sharply reduced. However, from I _on and V _th point of view, both of them are slightly undermined.

Fig. 10

According to the results obtained in Table  ² , I _on , I _off , I _on / I _off , Iamb, and V _th of both the proposed devices) GD–GaSb–EDTFET and GD–Al _0.1 GaSb–GaSb–EDTFET( have been improved as compared with the conventional Si-EDTFET device; therefore, both the proposed devices are the suitable candidates for analog and digital applications. By the comparison of the two proposed devices with each other and based on the results of Table  ² , transconductance and cut-off frequency curves (Fig.  ¹¹ ), it can be found that the GD–GaSb–EDTFET is more suitable for analog applications because of higher amounts of I _on , gm, f _T, and V _th than those of the GD–Al _0.1 GaSb–GaSb–EDTFET. In addition, I _off , I _amb , the I _on / I _off ratio, and the SS _P extracted from the GD–Al _0.1 GaSb–GaSb–EDTFET are better than the GD–GaSb–EDTFET, so the GD–Al _0.1 GaSb–GaSb–EDTFET is the more proper candidate for digital applications.

Fig. 11

Conclusion

In this paper, a junctionless tunnel field-effect transistor was simulated based on electrically doped concept using two-dimensional Silvaco TCAD. To increase on-state current, GaSb, a III–V semiconductor, was used which has narrow bandgap and high carrier mobility. On-state current with a value of 0.25 mA/μm at Vds = 1 V and Vgs = 1.2 V in case of GaSb–EDTFET was found to increase significantly compared to the conventional EDTFET. Then, the Gaussian-doping profile was used to reduce I _off and I _amb . Wherein I _amb is 9.9 × 10 ⁻¹⁹  A/μm, I _off is 1.2 × 10 ⁻¹⁸  A/μm, I _on is 2.5 × 10 ⁻⁴  A/μm, I _on / I _off ratio is 2.1 × 10 ¹⁴ , and the subthreshold swing (SS) is 56 mV/dec. In the process of improving the performance of the device at both the analog and digital applications, heterostructure source/channel interface was used; therefore, GaSb was allocated to source and AlGaSb to channel and drain regions. Then, the optimal Al composition for AlGaSb was founded to be around 10% ( x  = 0.1) by trading-off DC characteristics. The next Gaussian-doping profile was used in drain and channel. This Gaussian structure called the GD–Al _0.1 GaSb–GaSb–EDTFET has I _amb of 1.3 × 10 ⁻²³  A/μm, I _off of 1.7 × 10 ⁻¹⁹  A/μm, I _on of 6.2 × 10 ^{− 5}  A/μm, the I _on / I _off ratio of 3.6 × 10 ¹⁴ , and SS of 37 mV/dec, which has a remarkable improvement over the conventional Si-EDTFET. f _T and gm of devices were also investigated and the results demonstrated that the proposed devices were significantly better as compared with the conventional EDTFET. According to the numerical simulations, these proposed devices can also be the suitable candidates for analog and digital applications.