OICC Press International Journal of Nano Dimension 2228-5059 14 1 (January 2023) 2024 03 03 Numerical optimization of threshold voltage and off-current of a nano-scale symmetric double gate MOSFET based on the genetic algorithm: Various strategies compatible with device applications 10.22034/ijnd.2022.1963798.2166 EN Yazdan Karimi Pashaki Department of Electrical Engineering, Rasht Branch, Islamic Azad University, Rasht, Iran. 0000-0002-2111-5216 Seyed Ali Sedigh Ziabari Department of Electrical Engineering, Rasht Branch, Islamic Azad University, Rasht, Iran. 0000-0003-2048-6602 Abdollah Eskandarian Department of Electrical Engineering, Rasht Branch, Islamic Azad University, Rasht, Iran. 0000-0001-8788-4731 Ali Rahnamaei Department of Electrical Engineering, Ardabil Branch, Islamic Azad University, Ardabil, Iran. 0000-0002-8627-7259 Journal Article 2024 03 03 In this paper, we optimize the electrical characteristics of Nano-scale symmetric double-gate metal oxide semiconductor field effect transistors (DG-MOSFETs) for digital applications using a genetic algorithm. We use a single-objective genetic algorithm to optimize the threshold voltage (Vth) with a distinct analytical relationship. The optimization of the threshold voltage is accomplished for three cases with considering two structural variables of the oxide thickness (tox), the channel thickness (tsi), and the channel doping density (Na). The fourth case of optimization is done with considering these three variables. Comparison of these four cases illustrates that the best threshold voltage is 0.15 V for a channel doping concentration of 1.2×10 10 cm-3 and an oxide thickness of 1.49 nm. In addition, we optimize the OFF-current criterion based on the gate oxide thickness, the channel thickness, the channel doping concentration and the channel length and width. The optimization processes of the device are validated by simulating in SILVACO software. Furthermore, we use the two-objective genetic algorithm with the threshold voltage and the OFF-current objects for four structural variables including the gate oxide thickness, the channel layer thickness, and the channel length and width. This process is applicable to digital circuit design. To evaluate the accuracy of the proposed device optimization, the optimized device and other situations are simulated in SILVACO simulator. The optimized device illustrates the best treatment.