A low leakage and high-speed phase frequency detector-charge pump designed in nano dimension based CMOS technology

• Mohammad Amir Ansari * Email ORCID ¹
• Syed Hasan Saeed ORCID ¹
• Deepak Balodi ORCID ²
• Mohd. Nauman Khan ORCID ³

1. Department of Electronics & Communication Engg., Integral University, Lucknow, India
2. Department of Electronics & Communication Engg., BBD University, Lucknow, India
3. NXP India Pvt. Ltd., Bangaluru, India

Abstract

This research paper undertakes an innovative investigation into the conceptualization and execution of charge pump circuits that are specifically engineered in nano-dimension MOS transistor. In contrast to traditional Dickson-charge-pump models, the suggested configuration incorporates MOS transistors and anti-phase pumping clocks, which substantially increase output voltages and voltage pumping advantages. The PLL system's PFD, Charge Pump circuit, and PFD are dynamic components, as demonstrated by a thorough analysis of these elements on RF-simulation tool. The accuracy of the proposed methodologies through rigorous simulations, establishing them as innovative approaches for low-voltage circuitry. In addition to contributing to the advancement of knowledge regarding charge pump designs, the research offers significant insights into the synergistic functioning of these circuits within a PLL system. The simulation outcomes validate the efficacy of the novel charge pump configuration, presenting low spur attenuation, high phase margin and high loop gain for implementation in low-power electronic systems. With a particular focus on optimizing design parameters, investigating sophisticated materials and fabrication technologies, and striving for innovative applications in domains like communication devices. This study establishes a foundation for revolutionary advancements in the design of low-leakage circuits and provides opportunities for novel approaches to the evolving field of electronic technologies.

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