TY - EJOUR
AU - Razaz, Mohammad
AU - Seifossadat, Seyyed Ghodratollah
AU - Razaz, Morteza
AU - Joorabian, Mahmood
PY - 2024
DA - February
TI - A Digital Ground Distance Relaying Algorithm to Reduce the Effect of Fault Resistance during Single Phase to Ground and Simultaneous Faults
T2 - Majlesi Journal of Electrical Engineering
VL - 9
L1 - https://oiccpress.com/Majlesi-Journal-of-Electrical-Engineering/article/a-digital-ground-distance-relaying-algorithm-to-reduce-the-effect-of-fault-resistance-during-single-phase-to-ground-and-simultaneous-faults/
N2 - This paper intends to provide an algorithm of fault resistance compensation for digital ground distance relay considering the voltage and current transformer effects. Performance of the conventional ground distance relaying manner is adversely affected by different ground faults and also typical type, called a simultaneous open conductor and ground fault. The proposed scheme by using local-end data only, has shown satisfactory performances under wide variations in fault location, with different values of fault resistance and having positive and negative of power transfer angle. The presented method which has been carried out on the IEEE 14 bus benchmark is executed in PSCAD/EMTDC and MATLAB software and the results show the accurate performance of mention configuration.
IS - 1
PB - OICC Press
KW - Single Phase to Ground Fault, Simultaneous Open Conductor and Ground Fault, Digital Ground Distance Relaying, Fault Resistance Compensation, Voltage and Current Transformer 
EN -