Design of Multiple-Valued Interconnection Networks with Gate all Around Transistor for Smart Computer Networks

Abstract

In junctionless nanowire transistors, drain-channel-source doping is of the same type and level. Therefore, fabricating junctionless transistors is less complicated than inversion mode transistors. However, the reduced ratio of on current to off-state current (ION/IOFF) in junctionless nanowire transistors has made their operation difficult due to the high impurity scattering in the channel. The larger ION / IOFF ratio indicates an increase in transistor switching speed. In this study, the use of gate oxide engineering is proposed to increase of ION / IOFF ratio. The proposed oxide thickness is 1.5nm, which is a buffer layer with K = 5.7 and a thickness of 0.5nm, and the oxide with a high permittivity factor with K = 29 and a thickness of 1nm. The proposed structure is called GAA-JL-FET-with-oxide buffer layer. In GAA-JL-FET-with-oxide buffer layer, the ION / IOFF ratio has been improved by about 106 and 102 times compared to the structure with K = 3.9 and K = 7.5, respectively. Due to the high switching speed, the GAA-JL-FET-with-oxide buffer layer is applied to design the multiple-valued logic (MVL) interconnection network in the voltage mode for the first time using the mixed-mode tool in Silvaco software. The results reveal improving subthreshold parameters of the simulated device significantly enhance the average power, max delay and power delay product (PDP) of the proposed interconnection networks.